Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-06-18
2002-09-10
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S207000, C257S211000, C257S210000, C257S700000, C257S696000, C257S697000, C257S668000, C257S784000, C257S786000, C257S698000, C257S693000, C361S777000, C361S760000, C361S790000, C361S767000, C174S250000, C174S261000, C174S260000, C439S066000, C439S075000, C228S180100, C333S001000
Reexamination Certificate
active
06448640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to microelectronic device packaging. More particularly, the present invention relates to achieving a ball array and trace layout that enhances signal processing with the packaged microelectronic device. In particular, the present invention relates to a ball array and trace layout electrical enhancement technique that achieves a preferred difference in capacitance between any two ball pad sites and their respective traces for a printed circuit board ball array.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
As device operating speeds and the slew rates of driver switching simultaneously increase, the quality of the power V
cc
and ground V
ss
routing systems become a critical factor in the overall integrity of the system. In current designs, providing a source of charge in close vicinity of the switching activity is essential for the proper functioning of an overall integrated circuit system.
Prior art systems have been able to somewhat improve electrical performance with discrete capacitive components. These discrete capacitive components are usually mounted on a package substrate and then directly interconnected to the power V
cc
and ground V
ss
through conductive leads and vias. However, a major problem with using discrete capacitive components to decouple the power V
cc
and ground V
ss
traces is that they lose their effectiveness at high frequencies. Furthermore, there is often not enough space on the semiconductor package surface to mount a larger number of discrete capacitative components that may be necessary to decouple the system.
Although it is a common practice to add ground shielding around signal traces in order to reduce cross-talk between electrically conductive traces that communicate with an electronic device, ground traces themselves can induce cross-talk with adjacent signal traces. Another practice is to remove all excess metal between signal traces that is not being used for ground shielding. The placement of ground traces between signal traces increases the amount of real estate that is required upon a given substrate such as a printed circuit board (PCB). Another problem that exists is that signal traces can be configured in a given ball pad column that includes a ball array and signal traces that are configured into a different ball pad column in the ball array. These configurations lend themselves to an increased capacitance difference between any given ball pad and its respective trace and any other ball pad and its respective trace.
A phenomenon that occurs during overmolding of an integrated circuit chip package is flashing of encapsulation material between a substrate and a mold half. The often irregular wiring layout that may be the result of autorouting or hand routing of traces between bond wire pads in a bond wire pad column, and ball pads in a ball pad column, may cause some spacing between traces to be large enough to allow flashing of encapsulation material.
What is needed in the art is a ball array and trace layout electrical enhancement technique that overcomes the foregoing problems of prior art.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a ball array layout that minimizes the capacitance difference between any given ball pad and its nearest ground in any other given ball pad and its nearest ground. The ball array layout includes a plurality of buffer traces, each buffer trace having a perimeter. The buffer traces are disposed around a plurality of ball pads that are arranged in equally spaced columns and rows, respectively. The plurality of ball pads arranged in columns is disposed upon a substrate such as a printed circuit board (PCB), and each ball pad is the terminus of a conductive trace such as a signal trace, a ground trace, or a power trace. Each ball pad has an approximate center that is equally spaced from adjacent ball pads in both the respective columns and the respective rows. Each ball pad is aligned along a straight line to other ball pads in the respective column and to the other ball pads in the respective row. The present invention contemplates the columns to include a first column and a second column that lie parallel to each other. Each ball pad in the first column has a perimeter that is parallel to a first length of one of the plurality of buffer traces. At least one ball pad in the second column has a perimeter that is parallel to a second length of one of the plurality of buffer traces. Typically, the buffer trace second length is less than the buffer trace first length. In other words, the buffer trace may encircle most of the ball pads in the first column and may only partially encircle, to a lesser degree at least one of the ball pads in the second column.
In the present invention, a ball array and trace layout is configured to obtain a difference in capacitance of not more than about 0.06 picoFarads between any given ball pad and its corresponding trace and any other given ball pad and its corresponding trace. The present invention also relates to a ball array trace layout that minimizes capacitance between any given two ball pads and their respective traces by the placement of buffer traces near the ball pad and also adjacent at least one ground trace. The buffer trace is preferably a “floating” trace. In other words, the floating trace is not connected to ground, but rather provides a source to create inductance after a fashion that diminishes the inductive effect of any given ball pad and its corresponding trace upon any other given ball pad and its corresponding trace where the difference in capacitance between the two is preferably to be diminished below a certain design difference or “capacitative Delta”.
In the present invention, a “ball pad column” is defined as a plurality of serially adjacent ball pads that are arrayed with their approximate centers aligned with a straight line. Each ball pad is also spaced evenly along the straight line. Typically the even spacing is created by a series of ball rows, that create the even spacing, and that are arrayed orthogonal to the ball pad column. Each ball row is likewise a plurality of serially adjacent ball pads that are arrayed with their approximate centers aligned with a straight line that is orthogonal to the straight line that defines the alignment of the ball pad column.
According to the present invention, a ball array and trace layout is provided that includes a substrate and a ball array such as a fifty-four (54) ball pad array that is arranged in double sets of nine rows and three ball pad columns, each set being situated on an opposite side of a slot for board on chip (BOC) structures. After the routing of the traces between the ball pads and their respective bond wire pads, the present invention locates buffer traces adjacent to bond pads, where the buffer trace preferably lies proximate to a ground trace.
Where the capacitance in the ball array and trace layout is the highest, it is preferable that there will be a greater number of buffer traces. For example, an outer ball pad column or in other words a column that lies farthest from the center of the printed circuit board may have the highest capacitance and therefore preferably has thereat the highest number of buffer traces to respectively adjacent bond pads. A middle ball pad column, or in other words a ball pad column tha
Micro)n Technology, Inc.
Williams Alexander O.
Workman & Nydegger & Seeley
LandOfFree
Ball array layout in chip assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ball array layout in chip assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ball array layout in chip assembly will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2893127