Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2006-05-09
2006-05-09
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S017000, C438S018000, C356S445000, C324S765010
Reexamination Certificate
active
07041515
ABSTRACT:
The present invention includes a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal.One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer. The present invention also includes a system for selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure comprising a wafer fabricator, a planarizer, a layer profiler, an optical metrology device, and a selector for the selecting the design of underlying structure that yields a reflected metrology signal closest to the calibration metrology signal and where the planarized surfaces meet preset standard planarization characteristics.
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Jakatdar Nickhil
Niu Xinhui
Brewster William M.
Morrison & Foerster / LLP
Timbre Technologies, Inc.
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