Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2001-10-22
2004-06-01
Karlsen, Ernest (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S014000, C438S015000, C438S017000, C438S018000, C356S364000, C356S369000, C356S445000, C324S765010
Reexamination Certificate
active
06743646
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
This invention is in the field of manufacture of semiconductor devices. More particularly, this invention relates to a method and system of fabricating underlying structures to improve planarization characteristics of layers while minimizing introduction of random and/or systematic noise by the underlying structures to the metrology signal.
2. Related Art
As feature sizes in semiconductor devices shrink, photolithographic equipment requires that layers of a wafer be very flat or planar so that small feature dimensions are accurately patterned. Chemical mechanical planarization (CMP) is widely used in various semiconductor processing operations to planarize layers of a wafer. The polishing process typically uses an abrasive slurry and a combination of mechanical and chemical actions to planarize the layer surface.
CMP performance is affected by the density of underlying structures in a wafer, resulting in two phenomena called “dishing” and “erosion”.
FIG. 1A
is an architectural diagram illustrating the “dishing” effects of the CMP process on a layer of a wafer. In a stacked wafer structure
13
, the stack comprises a silicon layer or a substrate
11
and a dielectric layer or layers
9
, a metal seed layer
7
, and an interlayer dielectric (ILD)
5
, typically silicon oxide. The metal layer
3
, typically copper, aluminum, or tungsten, is planarized using a CMP process. Since the metal layer
3
is relatively softer than the ILD plus the chemical action of the CMP, a metal loss region
1
occurs, referred to as “dishing”.
FIG. 1B
is an architectural diagram illustrating the “erosion” effects of the CMP process on a layer of a wafer. In a stacked wafer structure
20
, an ILD layer
31
is fabricated above a substrate or previous layers (not shown). Another ILD layer
25
is fabricated above the etch stopper layer
29
. The metal layer
23
is planarized using a CMP process where a different polishing rate applies to the dense region
24
compared to the region with small features
22
. The difference in the polishing rate is most pronounced in the middle of the small feature region
22
, resulting in a concave-profile loss region consisting of loss of ILD and metal. This phenomenon, referred to as “erosion”.
One of the solutions used to solve the local pattern density effect is to use fill or dummy shapes. U.S. Pat. No. 5,278,105 entitled “Semiconductor Device with Dummy Features in Active Layers” to Eden, et al., discusses the use of fill shapes for correcting problems related to local pattern density
FIG. 2
is an architectural diagram illustrating the use of an optical metrology system to acquire critical dimension (CD) data off target periodic structures. The optical metrology system
40
consists of a metrology beam source
41
projecting a beam
43
at the target periodic structure
53
of a wafer,
43
mounted on a metrology platform
55
. The metrology beam
43
is projected at an incidence angle &thgr; towards the target periodic structure
53
. The reflected beam
49
is measured by a metrology beam receiver
51
. The reflected beam data
57
is transmitted to a metrology profiler system
53
. The metrology profiler system
53
compares the measured reflected beam data
57
against a library of calculated reflected beam data representing varying combinations of critical dimensions of the target periodic structure and resolution. The library instance best matching the measured reflected beam data
57
is selected. The profile and associated critical dimensions of the selected library instance correspond to the cross-sectional profile and critical dimensions of the features of the target periodic structure
53
. A similar optical metrology system
40
is described in U.S. Pat. No. 5,739,909, entitled “Measurement and Control of Linewidths in Periodic Structures Using Spectroscopic Ellipsometry.”, issued to Blayo, et al.
Two spectroscopic metrology techniques are used typically to measure target structures in a non-destructive manner: spectroscopic reflectometry and spectroscopic ellipsometry. In reflectometry, light intensities are measured. R=|r|
2
is the relation between the reflectance R and the complex reflection coefficient r. In spectroscopic ellipsometry, the component waves of the incident light, which are linearly polarized with the electric field vibrating parallel (p or TM) or perpendicular (s or TE) to the plane of incidence, behave differently upon reflection. The component waves experience different amplitude attenuations and different absolute phase shifts upon reflection; hence, the state of polarization is changed. Ellipsometry refers to the measurement of the state of polarization before and after reflection for the purpose of studying the properties of the reflecting boundary. The measurement is usually expressed as tangent (&PSgr;) and cosine (&Dgr;).
In spectroscopic metrology, the reflected optical signal is considered ideal when the underlying structure is unpatterned, i.e., like a unpatterned film or substrate. The presence of a pattern in the underlying structure may introduce random and/or systematic noise to the measured reflected optical signal. The source of random noise cannot be determined whereas systematic noise can possibly be determined and characterized. Significant random or systematic noise in the signal in turn skews the matching process of the measured reflected signal against the library of calculated reflected beam data, causing the match of the measured reflected signal to a different profile and/or different critical dimensions.
On the other hand, the underlying structure design may not introduce random and/or systematic noise to the measured reflected optical signal but the CMP characteristics of planarized layers might exceed ranges required by the application.
Thus, there is a need for identification of an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal.
SUMMARY OF INVENTION
The present invention is a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal.
One embodiment of the present invention is a method of optimizing the design of underlying structures in a wafer with one or more designs of pads of varying sizes and varying loading factors, comparing planarization characteristics of the underlying layers of the wafer to preset standard planarization characteristics, fabricating target structures in the target layer of the wafer, measuring a reflected metrology signal off a calibration test area to obtain a calibration metrology signal, the calibration test area having an unpatterned underlying structure, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with one or more designs of random shapes of varying sizes and varying loading factors in underlying layers of a wafer.
Still another embodiment of the present invention is a method of optimizing the design of underlying structures with one or more periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer. In one application, the angle relative to the direction of periodicity of the target periodic structure of the wafer is ninety degrees.
The present invention also includes a system for optimizing the selection of an underlying structure design that balances planarization and optical metrology objectives for a target structure comprising a wafer fabricator, a planarizer for planarizing a surface of an underlying la
Jakatdar Nickhil
Niu Xinhui
Karlsen Ernest
Morrison & Foerster / LLP
Timbre Technologies, Inc.
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