Balanced transformer-less amplifier and an offset detection...

Amplifiers – With periodic switching input-output

Reexamination Certificate

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C341S118000

Reexamination Certificate

active

06605990

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a balanced transformer-less (BTL) amplifier with output terminals for establishing a DC-connection to a load, comprising an offset detection system for detecting a differential DC-offset across the output terminals.
2. Description of the Related Art
An amplifier of the above mentioned kind is known from European Patent Application No. 1,006,650.
Presently, balanced transformer-less-amplifiers are often used, for instance, in audio systems for driving loudspeakers. Another application is in systems for driving actuators. These amplifiers have the advantage that they can generate large AC-power with a low voltage power supply and, because of the absence of output transformers or large DC-separating capacitors, they can easily be implemented in integrated circuit form. These advantages make them particularly useful as power amplifiers for use in car audio systems where they drive one or more loudspeakers.
However, the consequence of the DC-connection between the output terminals of the amplifier and the load, especially when this load has a low DC-impedance, is that large DC-currents may flow through the load if, for whatever reason, a DC-offset voltage exists between the output terminals of the amplifier. Such DC-offset voltage may e.g., be caused by a leaking DC-separation capacitor in the input of the amplifier or by an unbalance in the amplifier itself. The undesired DC-current, which may flow through the load, may be so large that the amplifier or the load (e.g., loudspeakers) is damaged or even that a serious fire-hazard occurs. In the balanced transformer-less-amplifier disclosed in the above mentioned European patent application, these problems are solved by the offset detection system, which then initializes an alarm system in case the DC-offset voltage exceeds a predetermined level. This prior art system periodically mutes the amplifier input signal, measures the DC-offset between the output terminals, and then, incase this DC-offset exceeds the predetermined level, actuates an alarm system or even shuts off the amplifier or disconnects the amplifier from the load.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an amplifier of the above referenced kind which has improved functionality. To that end, the amplifier of the present invention may therefore be characterized in that said offset detection system comprises an analog-to-digital converter for converting the signal voltage across the output terminals into a digital signal, a counter integrating the digital signal during a predetermined period of time, evaluation means for evaluating the result of said counter, and a digital-to-analog converter for generating, in response to the output of the evaluation means, an analog correction signal which is applied to the input of the amplifier for counteracting the DC-offset across the output terminals.
In the amplifier of the present invention, the entire signal across the output terminals, i.e., both the DC offset and the AC signal, is measured. This entire signal is digitized and counted during a predetermined sufficiently long period, so that the result of the counting after the predetermined period is in essence only dependent on the DC offset and not on the, for the measurement undesired, AC signal. The counting result may, after digital-to-analog conversion, be applied to the input of the amplifier as a DC feedback to reduce the offset. The amplifier of the invention dynamically reduces the DC offset, so that the dissipation in the load and in the amplifier output stages is substantially reduced. This is of particular importance in battery-operated amplifiers. Another advantage of the amplifier of the present invention is that the DC-offset measurement is carried out without interrupting the normal operation of the amplifier. Moreover, the digital solution is much more robust than analog integrating systems, which must operate with very small and fragile currents in order to be able to obtain usable time-constants at a reasonable chip area.
A preferred balanced transformer-less-amplifier, according to the present invention, is characterized in that the analog-to-digital converter is a sigma-delta modulator generating a 1-bit digital representation of the signal voltage across the output terminals of the amplifier. The sigma delta modulator is a simple and straightforward analog-to-digital converter, which has the additional advantage that a 1-bit digital representation of the analog signal is obtained which can be directly supplied to the counter. The counter may, e.g., be up-counted by the one-bits and down-counted by the zero-bits of the sigma-delta modulator. However, because the counting period and the bit-rate are predetermined, a simpler counter may be used in which the one-bits only count upwards while the zero-bits have no effect.
The output of the counter may be applied to a digital-to-analog converter for generating a DC feedback signal for application to the input of the amplifier. However, the count result still comprises a measurement error caused by the incomplete cancellation of the AC component across the output terminals of.the amplifier. Apparently, the count will be higher if the predetermined period ends when the AC signal is high than if the predetermined period ends when the AC signal is low. To remove this distortion and to make the offset control system responding less instantaneously, the balanced transformer-less amplifier of the invention may be advantageously characterized in that the evaluation means is arranged to generate a first signal when the result of the counter is above a first predetermined level, and a second signal when the result of the counter is below a second predetermined level, which is lower than the first level, in that a correction counter is provided which is decremented by a predetermined number when the evaluating means generates the first signal, and which is incremented by said predetermined number when the evaluation means generates the second signal, and in that the output of the correction counter is applied to said digital-to-analog converter.
The balanced transformer-less amplifier of the present invention may also be characterized in that the evaluation means is further arranged to generate a third signal when the result of the counter is above a third predetermined level, which is higher than the first level, and a fourth signal when the result of the counter is below a fourth predetermined level, which is lower than the second level, and that alarm means is provided which is actuated when the evaluating means generates said third or fourth signal. With this measure, it is assured that when the DC offset is so large, in a positive or negative direction, that a dangerous situation, either for the amplifier or for the load or even for the environment, may be feared, an alarm is activated, which is either audible or visible or both.
In the arrangement of the invention, it may occur that a DC offset exists within the offset detection system itself, especially in the analog-to-digital converter. This is, of course, undesirable because the result would be that a DC offset across the output terminals of the amplifier is generated instead of reduced. In order to avoid this situation, the balanced transformer-less amplifier of the present invention may be further characterized in that the output terminals are connected to the analog-to-digital converter through a polarity reversing analog switch, and that the output of the analog-to-digital converter is connected to the integrating counter through a polarity reversing digital switch which runs synchronously with the polarity reversing analog switch at a rate which is an integer multiple of the rate at which the counter results are generated. In this way, any fault in the count originating from the DC-offset of the analog-to-digital converter is compensated by an equal but opposite fault in the count before the predetermined count period is finished.
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