Balanced MOS capacitor with low stray capacitance and high ESD s

Details Balanced MOS capacitor with low stray capacitance and high ESD s Balanced MOS capacitor with low stray capacitance and high ESD s

1986-05-16

1988-07-19

James, Andrew J.

357 14, 357 236, H01L 2702

Patent

active

047588730

ABSTRACT:
A peaking capacitor for use with a differential input stage in an integrated circuit. The stage includes emitter degeneration resistors and a peaking capacitor coupled between the emitters. The capacitor is formed of MOS capacitors located over thinned oxide portions that lie within the confines of doped regions forming PN junctions with the semiconductor substrate. The doped regions are spaced apart by a distance that will result in depletion region reach-through at a voltage that is lower than the thinned oxide breakdown voltage. Thus, the structure is self-protecting and therefore resistant to electrostatic discharge damage. The capacitor that is formed has a value that is determined accurately by the area of the thinned oxide. It also has a low stray capacitance which makes it useful as a peaking capacitor.

REFERENCES:
patent: 4377029 (1983-03-01), Ozawa
patent: 4453090 (1984-06-01), Sempel
patent: 4626881 (1986-12-01), Kishi et al.

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