Balanced input buffer circuit for semiconductor memory

Details Balanced input buffer circuit for semiconductor memory Balanced input buffer circuit for semiconductor memory

1978-10-20

1981-07-21

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072385, H03K 326, H03K 500

Patent

active

042800706

ABSTRACT:
A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

REFERENCES:
patent: 3902082 (1975-08-01), Proebsting et al.

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