Balanced enhancement/depletion mode gallium arsenide buffer/comp

Details Balanced enhancement/depletion mode gallium arsenide buffer/comp Balanced enhancement/depletion mode gallium arsenide buffer/comp

1985-06-28

1987-03-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307530, H03K 19017, H03K 1704, H03K 19094, H03K 17687

Patent

active

046545476

ABSTRACT:
A complementary depletion/enhancement mode (CDEM) gallium arsenide circuit utilizes switching pull-up/pull-down circuits to achieve low power consumption, and makes use of gallium arsenide field effect transistors to achieve high speed. High yield depletion mode field effect transistors are used to implement the sometimes complex complementary logic function in a pass gate configuration. Low yield enhancement mode FETs are used in the closely coupled and spaced tracking circuit. Closely spaced enhancement mode FETs are used because of the likelihood of their having closely matched thresholds.

REFERENCES:
patent: 4438351 (1984-03-01), Schuermeyer
patent: 4441039 (1984-04-01), Schuster
patent: 4460978 (1984-07-01), Jiang et al.
patent: 4494020 (1985-01-01), Konishi

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