Balanced CMOS logic circuits

Details Balanced CMOS logic circuits Balanced CMOS logic circuits

1985-01-04

1986-10-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307279, 307471, H03K 19094, H03K 1920, H03K 1921, H03K 19017

Patent

active

046201173

ABSTRACT:
A logic gate circuit composed of CMOS transistors includes at least a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes. The logic gate circuit further includes at least a second pair of transistors formed of third and fourth transistors of the same conductivity as the first pair and having gate, source and drain electrodes. The source and drain electrodes of the first and second pairs are adapted to receive input signals. A pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary electrodes are provided. The gate of the fifth transistor is connected to the drain of the sixth transistor, and the gate of the sixth transistor is connected to the drain of the fifth transistor. The drain of the fifth transistor is further connected to the drains of the first and second transistors and to a true output terminal. The drain of the sixth transistor is further connected to the drains of the third and fourth transistors and to a complement output terminal. All of the first through sixth transistors are arranged on an integrated circuit substrate with topological regularity.

REFERENCES:
patent: 4350905 (1982-09-01), Sato
patent: 4367420 (1983-01-01), Foss et al.
Griffin et al., "Wired OR and AND Circuits for CVS and CMOS Logic"; IBM-TDB; vol. 27, No. 6, pp. 3200-3201; 11/1984.
"High Speed CVS Circuit"; Research Disclosure, May 1984, No. 241; Kenneth Mason Publications Ltd., England.

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