Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-07-15
2001-05-08
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S345000
Reexamination Certificate
active
06229348
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a balance-to-single signal converting circuit which converts balance (differential) signals into a single end signal.
2. The Related Art
A post filter for smoothing the signal waveform after DA (digital/analog) conversion is provided between a DAC (DA converter) and a data output terminal.
FIG. 9
shows a block diagram of a conventional post filter. This post filter comprises an SCF (Switched Capacitor Filter)
1
, an AAF (Anti Aliasing Filter)
102
and a reference voltage generator
3
. The reference voltage generator
3
generates a reference voltage
20
which is half the voltage of a power source voltage Vdd.
As shown in
FIG. 10
, the SCF
1
converts input signals Inp and Inn, which are signals equivalent to DA converted signals, into differential signals based on the reference voltage
20
(Vc), to output differential signals Vn and Vp.
The AAF
102
removes signals of a predetermined frequency or higher from the differential signals Vp and Vn so as to smooth these signals and converts these signals into a single end signal while amplifying the single end signal with a fixed amplification rate to output the signal as an output signal Vout. That is, the AAF
102
functions as a balance-to-single signal converting circuit having an low pass filter (LPF) characteristic.
As shown in
FIG. 11
, the AAF
102
comprises resistors
7
and
8
having resistance values r
1
, resistors
5
and
19
each having resistance values r
2
, capacitors
10
and
11
each having capacitance values C, and an operational amplifier
4
. The differential signal Vn is inputted into an inversion input terminal−of the operational amplifier
4
through the resistor
7
. The differential signal Vp is inputted into a non-inversion input terminal+of the operational amplifier
4
through the resistor
8
. The resistor
5
and the capacitor
11
are connected in parallel between an output terminal and the inversion input terminal of the operational amplifier
4
. Further, the resistor
19
and the capacitor
10
are connected in parallel between a reference voltage terminal receiving the reference voltage
20
and the non-inversion input terminal of the operational amplifier
4
.
For the sake of simplification of explanation, assuming that capacitance value C=0, the AAF
102
is a balance-to-single signal converting circuit without the LPF characteristic, and that the reference voltage generator
3
is the power source having an output impedance r, the circuit has the construction as shown in FIG.
12
. The output impedance r is represented as a resistor
81
, and a power source
82
is a direct current power source of an output voltage Vc.
In
FIG. 12
, a voltage Vx at a node x is expressed by equation 1.
Vx
=
r
2
×
Vn
+
r
1
×
Vout
r
1
+
r
2
(
1
)
Further, a voltage Vy at a node y is similarly expressed by equation 2.
Vy
=
r
1
×
Vc
+
(
r
+
r
2
)
×
Vp
r
1
+
r
2
+
r
(
2
)
Assuming that the open loop gain of the operational amplifier
4
is extremely large, the output signal Vout is expressed by equation 3.
Vout
=
1
+
r
2
/
r
1
r
1
+
r
2
+
r
{
r
1
×
Vc
+
(
r
+
r
2
)
×
Vp
}
-
r
2
r
1
Vn
(
3
)
This equation can be transformed into equation 4.
Vout
=
1
(
1
+
r
/
(
r
1
+
r
2
)
)
Vc
+
r
2
r
1
(
1
+
r
/
r
2
1
+
r
/
(
r
1
+
r
2
)
Vp
-
Vn
)
(
4
)
As understood from the first term of equation 4, if the output impedance r=0 does not hold, the central potential of the output signal Vout becomes a voltage resulting from multiplying the output voltage Vc of the power source
82
by 1/(1+r/(r
1
+r
2
). If r=0 holds, the central potential of the output signal Vout is the output voltage Vc of the power source
82
.
Further, as understood from the second term of equation 4, if r=0 does not hold, the voltage of the differential signal Vp becomes a voltage multiplied by (1+r/r
2
)/(1+r/(r
1
+r
2
)) and multiplied by the total gain (r
2
/r
1
). If ideally r=0 holds, the voltage of the output signal Vout is as expressed by equation 5.
Vout
=
Vc
+
r
2
r
1
(
Vp
-
Vn
)
(
5
)
As shown in the above equation 5, if the output impedance r of the reference voltage generator 3 is not “
0
”, variation of middle point potential and distortion occur in the output signal Vout.
For this reason, in one means for obtaining the output impedance r closer to “0”, the post filter has been arranged such that the circuit current of the reference voltage generator
3
is increased to lower the output impedance. In the alternative, as shown in
FIG. 13
, a bonding pad
92
is provided to output the reference voltage
20
as the output from the reference voltage generator
3
to an external terminal of the LSI, and the terminal is connected to a large capacity capacitor
91
having a capacitance value CL, to lower the alternating impedance.
However, in the former method, current consumption increases. In the later method, as the bonding pad
92
is provided, the chip area increases, and the capacitor
91
is required as an external component, which increases the cost.
FIG. 14A
shows an example of a circuit diagram of a reference voltage generator
23
having a concrete arrangement of the reference voltage generator
3
.
FIG. 14B
shows an equivalent circuit of the circuit in FIG.
14
A.
As shown in
FIG. 14A
, the reference voltage generator
23
comprises a p-channel MOS transistor
103
, an n-channel MOS transistor
104
and an output terminal outputting the reference voltage
20
. As shown in
FIG. 14B
, the equivalence circuit comprises a constant-current source
106
with a current Ib and a resistor
105
with a conductance g
mp
. Note that g
mp
is the conductance of the MOS transistors, and Vdd, a power source voltage.
From
FIG. 14B
, a voltage Vc
0
of the reference voltage
20
when no load is connected to the output terminal is as expressed by equation 6.
VcO=Vdd−Ib/g
mp
(6)
FIG. 15
shows a circuit diagram in a case where the reference voltage generator
23
replaces the reference voltage generator
3
in FIG.
12
. In this case, as the reference terminal is connected to load, the voltage Vc of the reference voltage
20
is as expressed by equation 7.
Vc
=
Vp
1
+
g
m
p
R
+
Vdd
-
Ib
/
g
m
p
1
+
1
/
g
m
p
R
(
7
)
This equation can be transformed into equation 8.
Vc
=
Vp
1
+
g
m
p
R
+
Vc0
1
+
1
/
g
m
p
R
(
8
)
From equation 8, it is understood that the reference voltage
20
output from the reference voltage generator
23
fluctuates depending on the differential signal Vp as input.
Further, as the reference voltage generator
23
comprises MOS transistors, flicker noise is added to the output. Flicker noise V
1/f
is expressed by equation 9.
V
1
/
f
2
=
K
f
CoxWL
Δ
f
f
(
9
)
Note that Cox is an oxide film capacity, L and W, a gate length and a gate width of the respective MOS transistors, and Kf, a flicker coefficient.
Note that assuming that R=r
1
+r
2
holds, working through the above equations 1 to 9, the voltage Vc of the reference voltage
20
is as expressed by equation 10.
Vc
=
Vp
1
+
g
m
p
R
+
Vc0
1
+
1
/
f
m
p
R
+
V
i
/
f
(
10
)
Note that the first term Vp/(1+g
mp
R) of equation 10 represents noise resulting from the differential signal Vp as input, the second term Vc/(1+1/g
mp
R) represents a fixed value of error in load driving, and the third term V
1/f
represents flicker noise. This fluctuation and noise of the reference voltage
20
directly appears as fluctuation and noise in the output signal Vout.
The above-described conventional balance-to-single signal converting circuits have the following problems:
(1) where the reference voltage generator is increased to lower the output impedance, consumption current increases;
(2) where a large capacity capacitor is added as an e
Kim Jung Ho
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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