Backup power circuit for biasing bit lines of a static semicondu

Details Backup power circuit for biasing bit lines of a static semicondu Backup power circuit for biasing bit lines of a static semicondu

1980-02-07

1982-06-29

Fears, Terrell W.

Static information storage and retrieval

Powering

Data preservation

365189, 371 66, G11C 1140

Patent

active

043375243

ABSTRACT:
A circuit is provided for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

REFERENCES:
patent: 3859638 (1975-01-01), Hume, Jr.
patent: 4051945 (1977-10-01), Fujimoto et al.
patent: 4122359 (1978-10-01), Breikss

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