Backside unlayering of MOSFET devices for electrical and...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21218, C257S492000, C156S345390

Reexamination Certificate

active

11242719

ABSTRACT:
A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

REFERENCES:
patent: 4411762 (1983-10-01), Kline
patent: 4503329 (1985-03-01), Yamaguchi et al.
patent: 5319197 (1994-06-01), Friedhelm
patent: 5653622 (1997-08-01), Drill et al.
patent: 5698474 (1997-12-01), Hurley
patent: 5916424 (1999-06-01), Libby et al.
patent: 5926688 (1999-07-01), Lee et al.
patent: 6211527 (2001-04-01), Chandler
patent: 6263566 (2001-07-01), Hembree et al.
patent: 6346768 (2002-02-01), Proudfoot
patent: 6570170 (2003-05-01), Moore
patent: 6590409 (2003-07-01), Hsiung et al.
patent: 2002/0072308 (2002-06-01), Kane et al.
patent: 2003/0073314 (2003-04-01), Skinner et al.
patent: H04-059049 (1992-02-01), None
patent: H06-209142 (1994-06-01), None
patent: 2001-518694 (2001-10-01), None
patent: 2002-500808 (2002-01-01), None
patent: 2004-536288 (2004-12-01), None
patent: 2001-168070 (2008-01-01), None
R. Desplats, F. Beaudoin, P. Perdu,CNC Milling and Polishing Techniques for Backside Sample Preparation, CNES-THALES Laboratory-18 avenue Edouard BELIN-31401 Toulouse Cedex 4-France, pp. 1-9.
R. Livengood, P. Winer, J.A. Giacobbe, J. Stinson, J.D. Finnegan,Advanced Micro-Surgery Techniques and Material Parasitics for Debug of Flip-Chip Microprocessor, Proceeding from the 25thInternational Symposium for Testing and Failure Analysis, Nov. 14-18, 1999, Santa Clara, CA, Intel Corporation, Santa Clara, CA, pp. 477-483.
J.P. Huynh, J.P. Shannon, R.W. Johnson, M. Santana, Jr., T.Y. Chu, M. Gonzalez,Backside FIB Device Modifications Through the BOX Layer of an SOI Device, Proceedings from the 28thInternational Symposium for Testing and Failure Analysis, Nov. 3-7, 2002, Phoenix, AZ, Advanced Micro Devices, Inc., Austin, TX, pp. 403-407.
V. Korchnoi, Dr. A. Fenigstein, A. Barger,Silicon Trenching Using Dry Etch Process for Back Side FIB and Probing, Proceeding from the 26thInternational Symposium for Testing and Failure Analysis, Nov. 12-16, 2000, Bellevue, WA, Intel Corporation, Israel pp. 559-565.
P.F. Ullmann, C.C. Talbot, R.A. Lee, C. Orjuela, R. Nicholson,A New Robust Backside Flip-Chip Probing Methodology, Proceedings of the 22ndInternational Symposium for Testing and Failure Analysis, Nov. 18-22, 1996, Los Angeles, CA, Schlumberger Technologies, San Jose, CA, pp. 381-386.
S. Silverman, R. Aucoin, J. Mallatt, D. Ehrlich,Laser Microchemical Technology; New Tools for Flip-Chip Debug and Failure Analysis, Proceedings from the 23rdInternational Symposium for Testing and Analysis, Oct. 27-31, 1997, Santa Clara, CA, Revise Inc., Burlington, MA, pp. 211-213.
C-L. Chiang, N. Khurana, D.T. Hurley, K. Teasdale,Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate, Proceedings from the 24thInternational Symposium for Testing and Failure Analysis, Nov. 15-19, 1998, Dallas, TX, Hypervision, Inc., Fremont, CA, Hexfet America, Temecula, CA, 1998 ASM International.
P. Perdu, R. Desplats, F. Beaudoin,Comparative Study of Sample Preparation Techniques for Backside Analysis, Proceedings from the 24thInternational Symposium for Testing and Failure Analysis, Nov. 12-16, 2000, Bellevue, WA, Toulouse, France, pp. 161-171.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Backside unlayering of MOSFET devices for electrical and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Backside unlayering of MOSFET devices for electrical and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Backside unlayering of MOSFET devices for electrical and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3948309

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.