Backside illuminated image sensor

Details Backside illuminated image sensor Backside illuminated image sensor

1999-11-17

2001-01-02

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S292000, C257S228000

Utility Patent

active

06169319

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to solid state image sensors. More specifically, the present invention relates to a method for fabricating backside illuminated image sensors and to a backside illuminated image sensor fabricated by the method.
RELATED ART
Solid state image sensors are used in, for example, video cameras, and are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a display.
CMOS image sensors first appeared in 1967. However, CCDs have prevailed since their invention in 1970. Both solid-state imaging sensors depend on the photovoltaic response that results when silicon is exposed to light. Photons in the visible and near-IR regions of the spectrum have sufficient energy to break covalent bonds in silicon. The number of electrons released is proportional to the light intensity. Even though both technologies use the same physical properties, all-analog CCDs dominate vision applications because of their superior dynamic range, low fixed-pattern noise (FPN), and high sensitivity to light.
More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography, coupled with advanced signal-processing algorithms, sets the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array. As discussed below, in frontside illuminated image sensors, this reduction of metal-line width exposes more silicon to light, thereby increasing light sensitivity. CMOS image sensors also provide greater power savings, because they require fewer power-supply voltages than do CCD imagers. In addition, due to modifications to CMOS pixels, newly developed CMOS image sensors provide high-resolution, low-noise images that compare with CCD imager quality.
CMOS pixel arrays are at the heart of the newly developed CMOS image sensors. CMOS pixel-array construction uses active or passive pixels. Active-pixel sensors (APSs) include amplification circuitry in each pixel. Passive pixels use photodiodes to collect the photocharge, whereas active pixels can include either photodiode or photogate light sensitive regions. The first image-sensor devices used in the 1960s were passive pixel arrays, but read noise for passive pixels has been found to be high, and it is difficult to increase the passive pixel array's size without exacerbating the noise. CMOS active-pixel sensors (APSs) overcome passive-pixel deficiencies by including active circuits (transistors) in each pixel.
FIG. 1
shows a CMOS APS image sensor circuit
100
that includes a pixel array
110
and control circuitry
120
.
Pixel array
110
includes a closely-spaced matrix of APS cells (pixels)
140
that are arranged in rows and columns. Pixel array
110
is depicted as a ten-by-ten array for illustrative purposes only. Pixel arrays typically consist of a much larger number of pixels (e.g., 804-by-1016 arrays). Moreover, the pixels may be arranged in patterns other than rows and columns. Each APS cell
140
of pixel array
110
includes a light sensing element that is capable of converting a detected quantity of light into a corresponding electrical signal at an output terminal
150
. The pixels in each row are connected to a common reset control line
123
and a common row select control line
127
. The pixels in each column are connected through respective output terminals
150
to an associated common column data line
130
.
Control circuitry
120
includes a row decoder
123
and sense amplifiers/registers
127
. A timing controller (not shown) provides timing signals to row decoder
120
that sequentially activates each row of APS cells
140
via reset control lines
124
and row select control lines
125
to detect light intensity and to generate corresponding output voltage signals during each frame interval. A frame, as used herein, refers to a single complete cycle of activating and sensing the output from each APS cell
140
in the array a single time over a predetermined frame time period. The timing of the imaging system is controlled to achieve a desired frame rate, such as 30 frames per second in video applications. The detailed circuitry of the row decoder
123
, sense amplifiers/registers
127
and timing controller is well known to one ordinarily skilled in the art. When detecting a particular frame, each row of pixels may be activated to detect light intensity over a substantial portion of the frame interval. In the time remaining after the row of APS cells
140
has detected the light intensity for the frame, each of the respective pixels simultaneously generates output voltage signals corresponding to the amount of light detected by that APS cell
140
. If an image is focused on the array
110
by, for example, a conventional camera lens, then each APS cell
140
generates an output voltage signal corresponding to the light intensity for a portion of the image focused on that APS cell
140
. The output voltage signals generated by the activated row are simultaneously provided to column output lines
130
via output terminals
150
. Column output lines
130
transmit these output voltage signals to sense amplifiers/registers
127
.
FIGS.
2
(A) and
2
(B) are simplified schematic and cross-sectional views showing a conventional frontside illuminated APS (image sensor) cell
140
(
1
). APS cell
140
(
1
) includes a photodiode
210
, a reset transistor
220
, an amplifier formed by a source-follower transistor
230
, and a select transistor
240
. Reset transistor
220
includes a gate connected to reset control line
124
(
1
), a first terminal connected to a voltage source V
DD
(e.g., 5 volts) that is transmitted on a voltage source line
223
, and a second terminal connected to a terminal of photodiode
210
and to the gate of source-follower transistor
230
via metal line
224
. Reset transistor
220
controls integration time and, therefore, provides for electronic shutter control. Source-follower transistor
230
has a first terminal connected to voltage source line
223
, a second terminal connected to a first terminal of select transistor
240
. Source-follower transistor
230
buffers the charge transferred to column output lines
130
from photodiode
210
, and provides current to charge and discharge capacitance on column output lines
130
more quickly. The faster charging and discharging allow the length of column output lines
130
to increase. This increased length, in turn, allows an increase in array size. Select transistor
240
has a gate connected to row select control line
125
(
1
) and a second terminal connected to column data line
130
(
1
) via output terminal
150
(
1
). Select transistor
240
gives half the coordinate-readout capability to the array. Although reset transistor
220
, source-follower transistor
230
and select transistor
240
would appear to increase the power consumption of APS cell
140
(
1
) over passive pixel cells, little difference exists between an active and a passive pixel's power consumption.
FIG.
2
(B) shows a simplified cross-section of conventional APS cell
140
(
1
). APS cell
140
(
1
) is formed in a P-type substrate
250
using known CMOS techniques. Photodiode
210
is formed in a first n-type diffusion (light sensitive) region
215
. Voltage source V
DD
is applied via voltage sou

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