Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-06-30
2003-11-25
Ton, Dang (Department: 2666)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06654370
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to transferring fragments between port cards and fabrics. More specifically, the present invention is related to transferring fragments between port cards and fabrics which accommodates for clock drift and transport delay.
BACKGROUND OF THE INVENTION
The switch is a packet/cell switch that is comprised of multiple fabrics and port cards. Multiple fabrics work on only a fragment of a packet at any one time. Each fabric needs to work independently with its own clock source but at the same time needs to be working on the same relative fragment of a packet at any logical time. Some method could be devised to have all fabrics work in lock step and use one global clock source. The problem with this approach would be that there would be a single point of failure using one clock source and it would be very difficult to meet timing between fabrics and port cards since transport delays of the clocks would be greater than the clock period. Worst case transport delay within the switch is 500 ns from one port card to a fabric and the clock period for a 125 MHz clock is 8 ns. As can be seen, there would be no way to know which rising edge of a clock at one destination corresponds to another rising edge at a different destination.
The Backplane Synchronizer in the switch has the main function of maintaining logical cell/packet ordering across all fabrics and port cards in a system that has clock drift and transport delay variances. This will allow fabrics and port cards to be sourced by an independent and free-running clock source. Cells/packets arriving at more than one fabric from different port cards need to be processed in the same logical order across all fabrics even if transport delays vary from each port card. If cell/packet logical ordering is not maintained, then cells/packets coming out of fabrics will have stripes of a particular cell/packet not match up and will not be able to be re-assembled by the Unstriper. The Synchronizer also handles alignment of byte lanes (due to having gigabit transceivers) that come from the same source but may have different transport delays. A switch which stripes data onto multiple fabrics and sends parity data to another fabric has been described in U.S. patent application Ser. No. 09/333,450, incorporated by reference herein. See also U.S. patent application Ser. No. 09/293,563 which describes a wide memory TDM switching system, incorporated by reference herein.
SUMMARY OF THE INVENTION
The present invention pertains to a packet switch. The switch comprises a plurality of port cards. Each port card has an unstriper which reassembles stripes of a particular packet. The switch comprises a plurality of fabrics. Each fabric operates on only a piece of the same respective fragment of a packet received from one of the plurality of port cards at any one time and allows the same respective fragments to be reassembled at one of the plurality of port cards. Each of the plurality of fabrics is connected to each of the plurality of port cards.
The present invention pertains to a method for switching packets. The method comprises the steps of sending a sync signal from a port card to a plurality of fabrics. Then there is the step of sending fragments of a packet as stripes to the respective plurality of fabrics. Next there is the step of operating on the fragments after they are received at each respective fabric by each respective fabric only after the respective fabric has received the sync signal.
In a preferred embodiment, the Backplane Synchronizer allows the switch to have multiple fabrics running on independent clock sources, to process data from multiple port card sources in a system that can have large inter-board clock skews and transport delay variances. The Backplane Synchronizer allows individual fabrics to process fragments of data that originate from the same source (port card) separately and to re-align the fragments from the fabrics again at a port card.
REFERENCES:
patent: 4958341 (1990-09-01), Hemmady et al.
patent: 5802052 (1998-09-01), Venkataraman
patent: 5805821 (1998-09-01), Saxena et al.
Bianchini, Jr. Ronald P.
Lepper Matthew
Quirke Jeff
Schulz Jeff
Spagnolo Gianfranco
Marconi Communications Inc.
Schwartz Ansel M.
Ton Dang
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