Backplane architecture for stackable ethernet repeater

Details Backplane architecture for stackable ethernet repeater Backplane architecture for stackable ethernet repeater

1995-06-07

1997-06-03

Olms, Douglas W.

Multiplex communications

Channel assignment techniques

Using a separate control line or bus for access control

370445, H04J 314

Patent

active

056362145

ABSTRACT:
A Class II stackable 100 Mbps Ethernet repeater architecture achievable by use of two different types of wired-OR interconnection in an Ethernet backplane, a Bus Transceiver Logic (BTL) wired-OR to selected control, data and clock lines, and a high-speed Transistor-Transistor Logic (TTL) which is wired-OR'ed together in three-level logic on a common activity signal line. The backplane has sufficiently low signal latency to permit two logical repeaters to be connected together with at least eight stackable repeater modules in each logical repeater, each repeater module having thirteen to sixteen station ports to support as many as 254 stations in a 100 Mbps environment with a diameter of 205 meters, which is up to 8.5 times greater than previously achievable.

REFERENCES:
patent: 5122691 (1992-06-01), Balakrishnan
patent: 5301303 (1994-04-01), Abraham et al.
patent: 5388099 (1995-02-01), Poole
patent: 5517520 (1996-05-01), Chi

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