Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-01-24
2001-01-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S200000
Reexamination Certificate
active
06178117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to microelectronic nonvolatile memory integrated circuits. Even more specifically, this invention relates to a method of correcting for the loss or gain of charge in memory bits in nonvolatile memory devices.
2. Discussion of the Related Art
There are several examples of nonvolatile memory integrated circuits. One such nonvolatile memory integrated circuit is a microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device that includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to erase all of the cells as a block, to read the cell, to verify that the cell is erased or to verify that the cell is not overerased.
The memory cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of all the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the source causing hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the respective programming voltages, the injected electrons are trapped in the floating gate creating a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 5 volts to the wordline to which the control gate of the cell is connected, applying 1 volt to the bitline to which the drain of the cell is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. These applied voltages cause the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. In another arrangement, applying a negative voltage on the order of −10 volts to the control gate, applying 5 volts to the source and allowing the drain to float also erases a cell. A further method of erasing a cell is by applying 5 V to the P-well and −10 V to the control gate while allowing the source and drain to float.
A problem with the flash EEPROM memory devices is that due to manufacturing tolerances, some cells that have been programmed can lose charge over time to the point that they no longer will read as being programmed. Other cells that have been erased can gain charge over time to the point they no longer will read as being erased. Because there is no way to determine the point at which the individual cells will cause errors during read because of charge loss or gain, the lifetime of the memory may be unnecessarily shortened to ensure that errors during read do not occur.
Therefore, what is needed is a method to check each cell for charge loss or gain as to correct the charge gain or loss in each individual memory cell to prevent the stored data from being corrupted.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of checking each memory bit for charge gain or loss and for correcting each individual memory bit that has either a charge gain or a charge loss.
In accordance with an aspect of the invention, an unused sector in a nonvolatile memory device is identified and each memory bit in the unused sector is checked to identify memory bits having a charge gain or a charge loss. An erase pulse is applied to each erased memory bit having a charge gain and a programming pulse is applied to each programmed memory bit having a charge loss.
In accordance with another aspect of the invention, a threshold voltage of each memory bit is stored in a latch. The threshold voltage stored in the latch is compared to a charge loss threshold voltage if the bit is a programmed memory bit and if the threshold voltage of the programmed memory bit is less than the charge loss threshold voltage, a programming pulse is applied to the memory bit.
In accordance with another aspect of the invention, the threshold voltage stored in the latch is compared to a charge gain threshold voltage if the bit is an erased memory bit and if the threshold voltage of the erased memory bit is greater than the charge gain threshold voltage, an erase pulse is applied to the memory bit.
The described method thus provides a method of correcting for the loss or gain of charge in nonvolatile memory bits in nonvolatile memory devices.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5689459 (1997-11-01), Change et al.
patent: 5699298 (1997-12-01), Shiau et al.
patent: 5717632 (1998-02-01), Richart et al.
patent: 5745410 (1998-04-01), Yiu et al.
Advanced Micro Devices , Inc.
Le Thong
Nelms David
Nelson H. Donald
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