Background comparator offset calibration technique for flash...

Details Background comparator offset calibration technique for flash... Background comparator offset calibration technique for flash...

2006-06-20

2006-06-20

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000

Reexamination Certificate

active

07064693

ABSTRACT:
A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed for using in mixed-signal integrated circuit design in particular on the high-speed analog-to-digital converter circuit. Without affecting the operation of the comparator, the disclosure is directed at reducing the unpredictable input offset voltage originated from the variation of process parameters and environmental factors. The background-calibrated comparator includes a random chopping comparator, a calibration processor, and a random sequence generator. The background-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, a thermometer code edge detector, and a set of digital encoders.

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H. van der Ploeg, G. Hoogzaad, et al. “A 2.5-V 12-b 54-Msample/s 0.25-mm CMOS ADC in 1-mm2 with mixed signal chopping and calibration,” IEEE J. Solid-State Circuits, vol. 36, Dec. 2001, pp. 1859-1867.

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