Background calibration system for calibrating non-linear...

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

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C341S118000, C341S155000

Reexamination Certificate

active

07821435

ABSTRACT:
The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier.

REFERENCES:
patent: 6784814 (2004-08-01), Nair et al.
patent: 7187310 (2007-03-01), El-Sankary et al.
B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, Dec. 2003, pp. 2040-2050, vol. 38, No. 12.
J. P. Keane, P. J. Hurst, and S. H. Lewis, “Background interstage gain calibration technique for pipelined ADCs,” IEEE Trans. Circuits Syst. I, Jan. 2005, pp. 32-43, vol. 52, No. 1.
J. Yuan, N. Farhat, and J. V. der Spiegel, “A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration,” in Proceedings of the IEEE Custom Integrated Circuits Conference, Sep. 2005, pp. 399-402.
C. R. Grace, P. J. Hurst, and S. H. Lewis, “A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, May 2005, pp. 1038-1046, vol. 40, No. 40.
A. Panigada and I. Galton, “Digital background correction of harmonic distortion in pipelined ADCs,” IEEE Trans. Circuits Syst. I, Sep. 2006, pp. 1885-1895, vol. 53, No. 9.

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