Backgate biased synchronizing latch

Details Backgate biased synchronizing latch Backgate biased synchronizing latch

1999-12-16

2003-01-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000, C326S033000, C326S094000

Reexamination Certificate

active

06512406

ABSTRACT:

FIELD OF INVENTION
The field of the invention relates to semiconductor circuit design generally and, more specifically, the use of back gate biasing in order to reduce the mean propagation delay caused by metastability within a latch core. BACKGROUND OF THE INVENTION
FIG. 1
b
shows an embodiment of a latch circuit
100
having the truth table
101
indicated. As shown in
FIG. 1
a
, the latch circuit refuses to latch if a full data pulse
190
appears after a rising clock edge
191
or if a full data pulse
192
appears before a falling clock edge
193
. Referring to
FIG. 1
b
, when the RESET input
102
is low, the gate
103
of NFET transistor i
46
is high which turns transistor i
46
active (or “on”). When transistor i
46
is on it forms a short circuit to ground
104
a
which provides a logic low signal at the gate node
105
of PFET transistor i
69
, and NFET transistor i
71
. The combination of transistors i
69
and i
71
forms an inverting circuit
108
, thus the logic low at their gate node
105
, produces a logic high at node
106
. The logic high at node
106
is coupled to the inverting circuit formed by transistors i
83
, i
84
resulting in a logic low at the latch circuit output
107
. Thus, as seen in the truth table
101
, when the RESET input
102
is low, the latch circuit output
107
is typically low (one exception may occur if CLOCK
113
is high and DATA
112
is high-in which case the output
107
is usually high).
Note the combination of transistors i
70
and i
72
form another inverting circuit
109
. The interlocking or back-to-back relationship between inverting circuits
108
,
109
(i.e., referring to the inset, the output of each inverting circuit is coupled to the input of the other) forms a latch core
111
. Latch cores, such as latch core
111
, securely hold a data bit.
Node
106
is driven to specific states for each of the various combinations at input nodes RESET
102
, DATA
112
, and CLOCK
113
. When the RESET input
102
is high, transistor i
46
is inactive (or “off”) since its gate
103
is a logic low. When i
46
is off, the latch core
111
holds its value (i.e., does not change its logical states), since the transistor i
46
drain node
120
is controlled by the output of inverter
109
and no channel is formed within transistor i
46
. Qo is the term used in the truth table
101
to indicate that the specific input combination produces no change at latch circuit output
107
. Thus when the RESET input is logic high, the latch output
107
is changed only if so affected by DATA and CLOCK inputs
112
,
113
.
Another way of stating the above is that the DATA and CLOCK inputs
112
,
113
are only useful when the RESET input
102
is high. This is indicated in the truth table
101
. When the CLOCK input
113
is logic high, the output of inverting circuit
114
(formed by the combination of transistors i
88
and i
89
) is low which places NFET transistor i
64
off. When transistor i
64
is off the state of transistor i
3
is irrelevant in terms of its affect on node
106
. That is, node
106
is driven by the output of inverter circuit
108
when transistor i
3
is off. Thus when the CLOCK input
113
is high and the RESET input
102
is high, the latch output
107
remains unchanged as indicated in the truth table
101
by Qo.
When the CLOCK input
113
is low, the transistor i
64
gate voltage is high turning transistor i
64
on. This places a ground voltage at the source
121
of transistor i
3
. In this case, if the DATA input
112
is low, transistor i
3
is off which, again, leaves node
106
unchanged as it is driven by inverting circuit
108
. However, if the DATA input
112
is high, transistor i
3
is on which ideally drives node
106
low (since the active channels of transistors i
3
, i
64
form a short circuit to ground
104
b
). This forces the inverter
109
output high which, being coupled to the input of inverter
108
keeps node
106
low. Thus regardless of the original logic state of node
106
, when the RESET input
102
is high, the CLOCK input
113
is low and the DATA input is low the latch circuit output is unchanged. And, as indicated in the truth table
101
, when RESET input
102
is high, the CLOCK
113
is low and the DATA input is high, the latch circuit output is high.
In some cases when the latch circuit
100
observes proximately timed transitions in DATA
112
and CLOCK
113
, the small skew between DATA
112
and CLOCK
113
causes node
106
and the output of inverting circuit
109
to quasi-balance at a voltage level that is incapable of flipping either inverter circuit
108
,
109
. As a result, both nodes simply sit at this voltage level and the latch does not flip until a runaway iterative process flips both inverters
108
,
109
.
SUMMARY OF THE INVENTION
An apparatus comprising a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net.


REFERENCES:
patent: 5594381 (1997-01-01), Bingham
patent: 5600588 (1997-02-01), Kawashima
patent: 5739702 (1998-04-01), Shigehara et al.
patent: 5764007 (1998-06-01), Jones
patent: 5917365 (1999-06-01), Houston
patent: 6031778 (2000-02-01), Makino et al.
“A 1V DMOS Digital Circuits with Double-Gate-Driven MOSFET,” Wong, Louis S. Y. and Rigby, Graham A., ISSCCEE, Feb. 8, 1997.

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