Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-10-31
2004-04-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S117000
Reexamination Certificate
active
06727115
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to connecting chips or dies to substrates, and, particularly, electrically connecting and bonding the back-side of a die directly to a substrate and protecting conductive traces from contaminants in semiconductor and thermal inkjet printer applications.
BACKGROUND OF THE INVENTION
One of ordinary skill in the art in semiconductor technology readily understands that integrated circuits (ICs) are formed in and on wafers made from semiconductor material(s) as one of the basic steps of microchip fabrication. The area on a wafer occupied by a discrete IC is called a chip or a die. In the wafer fabrication process, the discrete ICs are formed in and on the wafer surface and are wired together. The resulting circuit is protected with a final sealing layer. Following wafer fabrication, the chips on the wafer are complete, but in untested wafer form.
To use a chip for its intended purpose, such as part of an electronic circuit or electronic product, the chip is packaged in a usable form that provides a lead system to connect the chip to a circuit board or directly to an electronic device. Moreover, the package provides physical protection for the fragile chip, including environmental protection and heat dissipation. An example of a packaged chip
2
is shown in Prior Art FIG.
1
.
In the packaging process, the wafer is separated into individual chips or dies through sawing, etching, or scribing. The die needs to be electrically connected and bonded to its substrate prior to packaging and use. This has been accomplished by using an adhesive, such as a gold/silicon eutectic or an epoxy adhesive, to attach the die to the substrate. Electrical connections are then made on the front-side of the die, such as the individual wire bonding shown in Prior Art
FIG. 2
, where up to hundreds of thin wires
4
(only one shown) electrically connect a interconnect pad
6
on the front-side
10
of chip
2
to a lead
8
on a substrate or package
12
(shown in FIG.
1
). The individual wires are expensive and fragile. Moreover, the profile height is relatively high compared to other bonding techniques, which makes this method undesirable for small/shallow package applications.
Another known means for electrically connecting a die to a substrate is via a flip-chip/bump process. This is best seen in
FIGS. 3 and 4
, where a metal bump
14
is deposited on each bonding pad on the front-side
10
of chip
2
in lieu of wires. The chip
2
is connected to the substrate
16
by flipping the chip
2
over and soldering the bumps
14
to corresponding substrate inner leads
18
. This technique has a lower profile than the wire bonding, but is still not ideal for many applications, and, particularly, in corrosive applications.
Referring to Prior Art
FIG. 5
, another well-known means for electrically connecting a die to a substrate, and most popular in thermal inkjet printhead applications, is the TAB (tape automated bonding) technique. TAB uses flexible continuous tape
20
containing many individual lead systems on the tape. The bond is complete when heat and pressure (such as from a thermode shown at
22
) is applied to the tape
20
to physically and electrically bond the inner leads onto the interconnect pads or bonding pads
24
of chip
26
. TAB is used extensively in low profile devices. Also, this technique is fast and cost-effective. A major drawback of TAB is the deterioration of the adhesives, and, ultimately, the electrical connections/bonds over time when exposed to corrosive contaminants.
As alluded to above, TAB connections are heavily used in thermal inkjet printer technology because of the low profile that can be obtained with TAB, as well as the speed in which the bonds can be made between the die and substrate during manufacture. Prior Art
FIGS. 6-13
are disclosed herein to better educate the reader as to how TAB bonds have been conventionally used in thermal inkjet printers.
FIGS. 6-12
are part of the common assignee's U.S. Pat. No. 5,420,627 (inventors Keefe et al.), granted May 30, 1995, and entitled ‘Inkjet Printhead.”
Exemplary of the TAB circuits in thermal inkjet printheads, as can be see in
FIG. 9
, a printhead
28
comprising a TAB circuit
30
is incorporated into a print cartridge
32
. The printhead, or pen, consists of a fluid (ink)-ejecting substrate
34
having a plurality of nozzles
36
within an orifice plate
38
. The fluid-ejecting substrate is fluidically coupled to a reservoir of ink ((either within the cartridge, shown generally at
40
, or externally (not shown)). Contact pads
42
carry electrical signals from a microprocessor in the printer to the IC in the die of the printhead to send signals, in the form of current, to specific resistors (not shown) associated with the nozzles
36
, typically one nozzle per resistor. The control of specific resistors forms droplets of ink
44
that are ejected through the nozzles
36
onto print media, such as paper. The resistors also heat the droplets such that they dry on contact or near contact on the print media.
The TAB circuit
30
comprises a flexible tape
46
. The back-side of the tape
48
includes a plurality of conductive traces
50
, which are commonly copper and highly-susceptible to corrosion. Substrate
52
, which contains a plurality of the heater resistors, is mounted onto the back-side of tape
46
. The substrate
52
is bonded and electrically connected to traces on the tape via electrodes, which would be beneath windows
54
.
The interconnect or interconnect pads are sealed or encapsulated, such as enumerated at
56
in
FIG. 11
, to protect the integrity of the electrical connection. Thus, encapsulation is typically used over the interconnect pads. This forms an encapsulant bead
58
, which is exemplified in FIG.
13
. The encapsulant bead has a profile height of “h” (in the range of 0.5 mm) that must be taken into account when positioning the fluid-ejecting substrate of the printhead relative to the print media.
Referring also to
FIG. 27
, it is desirable to have the print media be as physically close to the nozzles of the fluid-ejecting substrate as possible (also called pen to paper spacing or PPS), taking into account that the print media type will require some clearance for issues such as paper cockle, envelope seams, and the like, (which is also in the range of 0.5 mm). By eliminating unnecessary encapsulation or bead height, or other profile height within the printhead, the conventional distance between the printhead and print media of 1.0 mm can be reduced by as much as approximately 0.5 mm. This close tolerance is highly desired as print quality is enhanced when the distance between the fluid-ejecting substrate and the print media is reduced.
SUMMARY OF THE INVENTION
The present invention is directed to a method for electrically connecting a chip or die having active circuitry to a substrate, whether in semiconductor applications or in thermal inkjet printer applications, without the need for TAB as a bonding means between the die and substrate. Each die includes a front-side and a back-side. At least one through-hole is formed within the die between the front-side and the back-side. Each aperture is aligned with a conductive trace on the substrate. A conductive member is inserted through a corresponding through-hole from the back-side of the die. One end of the conductive member is electrically connected to its corresponding trace. The conductive member is inserted through the die such that other end of the conductive member is exposed at the front-side of the die to contact an interconnect pad that is electrically connected to the active circuitry of the die.
The back-side of the die is bonded and sealed to the substrate about the at least one conductive member. A sealant is applied to the interconnect pad to substantially hermetically seal the electrical connection between the active circuitry and the trace.
REFERENCES:
patent: 5137836 (1992-08-01), Lam
patent: 5416971 (1995-05-01), Hegazi et al.
patent: 5608264 (1997-03-01),
Elms Richard
Hewlett--Packard Development Company, L.P.
Owens Beth E.
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