Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-12-22
2002-04-09
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S223000, C257S224000, C257S230000, C257S250000
Reexamination Certificate
active
06369415
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a back side thinning charge-coupled device (CCD) with high speed channel stop.
A conventional unthinned CCD comprises a substrate of p+ silicon on which a layer of p− silicon is grown epitaxially. Using conventional implantation techniques, n− channels are formed in the front side of the epitaxial layer. The n− channels include signal channels for parallel (or vertical) registers and a signal channel for at least one serial (horizontal) register. P+ lateral channel stops are implanted between the signal channels of the parallel registers. An electrode structure is deposited over the front side of the epitaxial layer for controlling transfer of charge packets through the parallel registers and the serial register.
In order to transfer charge packets in the parallel registers of the conventional unthinned CCD, it is necessary to supply holes to the parallel registers so that displacement current can flow. For high speed operation, there must be a low resistance path for supplying holes to the parallel registers.
The p+ substrate is a good conductor and is connected to ground and therefore can sink and source holes efficiently. Although the p− epitaxial layer does not have a high conductivity, the geometry of the conventional unthinned device is such that there is a low resistance path between the substrate and the p+ channel stops, and accordingly holes can be supplied efficiently from ground to the n− signal channels via the p+ substrate, the p− epitaxial layer and the p+ channel stops.
The p+ lateral channel stop between two adjacent signal channels of the parallel registers isolates charge packets in one parallel register from an adjacent parallel register. Instead of providing a lateral channel stop between each two adjacent signal channels of the parallel registers, the channel stops may alternate with lateral antiblooming drains. A lateral antiblooming drain between two signal channels is formed by two p− barriers adjacent the signal channels respectively and an n+ region between the two p− barriers. The doping level in the p− barriers is selected so that the p− regions are depleted and the barriers have a slightly lower potential than the maximum potential barrier created in the signal channel by clocking the electrode structure. If the quantity of charge that is supplied to a transfer cell in the signal channel exceeds the capacity of the cell, excess charge will overflow the p− barrier into the n+ drain instead of overflowing into the adjacent transfer cell of the signal channel.
In the conventional unthinned CCD, the lateral antiblooming drains are connected to a reference potential through an n+ region which extends perpendicular to the signal channels outside the active area of the device. This arrangement is subject to disadvantage because it precludes the possibility of having dual serial registers, at opposite ends respectively of the parallel register.
In order to fabricate a back side thinned CCD, material of the p+ substrate is removed from the device at its back side so that the back side of the thinned device is much closer to the front side than is the case in an unthinned device. During thinning, material may be removed from the back side as far as the p− epitaxial layer. Consequently, the p+ lateral channel stops are no longer connected to ground through the low resistance path of the p− epitaxial layer and p+ substrate. The p+ lateral channel stops are connected to the p+ substrate outside the active area of the CCD and therefore can supply holes to the parallel registers, but the impedance of the p+ lateral channel stops is so high that they cannot provide holes at a sufficient rate for high speed operation of the device. Further, a potential difference exists along the p+ lateral channel stops so that the p+ channel stops do not efficiently ground the p− epitaxial layer. Consequently, the potential of the p− layer varies as the electrode structure is clocked, and this reduces the full well capacity of the transfer cells in the signal channel.
SUMMARY OF THE INVENTION
According to the present invention there is provided a back thinned CCD having at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.
REFERENCES:
patent: 3869572 (1975-03-01), Carter
patent: 4593303 (1986-06-01), Dyck et al.
patent: 4603342 (1986-07-01), Savoye et al.
patent: 5754228 (1998-05-01), Dyck
Munson Gene M.
Pixel Vision, Inc.
Smith-Hill John
Smith-Hill and Bedell
LandOfFree
Back side thinned CCD with high speed channel stop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Back side thinned CCD with high speed channel stop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Back side thinned CCD with high speed channel stop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2838543