Back end IC wiring with improved electro-migration resistance

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S765000, C438S622000, C438S627000, C438S629000, C438S637000, C438S651000

Reexamination Certificate

active

07119440

ABSTRACT:
A multi-level semiconductor device wiring interconnect structure and method of forming the same to improve electrical properties and reliability of wiring interconnects including an electromigration resistance and electrical resistance, the method including forming a dielectric insulating layer over a conductive portion; forming a via opening in closed communication with the conductive portion; forming a first barrier layer to line the via opening; forming a layer of AlCu according to a sputtering process to fill the via opening to form an AlCu via including a portion overlying the first dielectric insulating layer; and, photolithographically patterning and dry etching the portion to form an AlCu interconnect line over the AlCu via.

REFERENCES:
patent: 6159842 (2000-12-01), Chang et al.
patent: 6355558 (2002-03-01), Dixit et al.
patent: 6376353 (2002-04-01), Zhou et al.
patent: 2004/0000719 (2004-01-01), Matsubara et al.

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