Back-drive circuit protection for I/O cells using CMOS process

Details Back-drive circuit protection for I/O cells using CMOS process Back-drive circuit protection for I/O cells using CMOS process

2006-07-04

2006-07-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S108000

Reexamination Certificate

active

07071764

ABSTRACT:
In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.

REFERENCES:
patent: 5467031 (1995-11-01), Nguyen et al.
patent: 6249410 (2001-06-01), Ker et al.

Affiliated with

Also associated with

Rating

Back-drive circuit protection for I/O cells using CMOS process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Back-drive circuit protection for I/O cells using CMOS process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Back-drive circuit protection for I/O cells using CMOS process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3604645