Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-07-26
2004-10-26
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000, C327S541000
Reexamination Certificate
active
06809574
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method and system for providing back-drive circuit protection for I/O cells in a CMOS integrated circuit device.
BACKGROUND OF THE INVENTION
A typical integrated circuit device (IC) includes a core region
100
, as illustrated in
FIG. 1
, and one or more functional elements or packages such as analog support/conversion circuitry
102
. These are connected through an I/O interface
104
to pads
106
that allow the IC to be connected externally to other devices. The voltage levels vary for different portions of the IC, thus requiring special consideration to avoid exposing the various portions of the IC to excessive voltage levels. For instance, the core, I/O interface, and external circuitry to which the pads of the IC connect, typically will each support different voltages. Even within a typical CMOS core, voltages vary depending on the process used. For example, a 0.25 &mgr;m process supports voltage levels of the order of 2.5 V±10%; a 0.18 &mgr;m process supports voltage levels of the order of 1.8 V±10%; a 0.15 &mgr;m process supports voltage levels of the order of 1.5 V±10%, and a 0.13 &mgr;m process supports voltage levels of the order of 1.2 V±10%. In contrast, the I/O interface needs to support 3.3 V typically. For ease of understanding the input voltage levels to the core have been identified as VDD and VSS while those for the I/O interface are indicated as VDDIO and VSSIO. Furthermore, the pads may be connected to circuitry operating in the 5 V range. For example, where the IC drives a PCI bus, it is important that the IC can withstand the higher voltages of the system that it is supporting. In order to supply the higher voltage, a dual gate process involving the use of thick gate oxides is commonly used in the case of sub-micron CMOS.
The main concern arises under stress mode conditions when the pads are exposed to high voltages (approximately 5.5 V) by the external circuitry. Furthermore, different stress mode conditions may be identified. In particular, it is common to reduce VDD and VDDIO to 0V when the circuitry of the IC is not in use, thereby conserving energy.
An IC may typically be operated in one of three modes: (a) Normal mode, in which the core is powered up and drives the pads; (b) Tolerant mode, which is a stress mode in which the pads are raised up to 5.5 V, while the core and I/O interface are powered up (VDD and VDDIO are high); (c) Back-drive mode, which is a stress mode in which the pads are raised up to 5.5 V, while the core and I/O interface are powered down (VDD and VDDIO are low). Thus back-drive refers to the 5.5 V tolerant interface when there are no power supplies asserted. This condition becomes particularly important in the case of sub-micron CMOS, dual gate process technology in which the oxide breakdown and drain-source junction breakdown is about 3.8 V. Back-drive I/Os have to tolerate 5.5 V at the pads with and without power supplies asserted (commonly referred to as 5V tolerant level due to the 5V±10% tolerance). However, under stress mode, sub-micron dual gate devices tend to experience problems such as oxide breakdown, drain-source junction breakdown, current flow to VDDIO, and well charging due to the parasitic internal diode structure of CMOS devices.
FIG. 2
shows a simple I/O interface driver circuit comprising a p-channel (PMOS) pull-up transistor
200
and a n-channel (NMOS) pull-down transistor
210
which accommodate different load conditions under normal operation. When PMOS
200
is on and NMOS
210
is off, the load can be charged up to VDDIO. On the other hand, when PMOS
200
is off and NMOS
210
is on, the load can discharge to VSSIO. Thus the driver's output to the pad will, under normal operation, provide voltages ranging from VDDIO to VSSIO. Since VDDIO (3.3 V±10% under normal operation) is applied to both gates of the transistors
200
,
210
one transistor will always be off, thereby avoiding shoot-through current through the driver transistors
200
,
210
.
However, under 5V tolerant mode and back-drive mode, the pad
212
is raised to 5.5 V. In order to avoid gate oxide breakdown the voltage drop from drain to gate must not exceed 3.8 V. Similarly, to avoid junction breakdown, the voltage drop from drain to source must not exceed 3.8 V. Furthermore, it is necessary to isolate the receiver input circuitry from the pad under these stress modes. Since, during stress mode the pad
212
cannot be driven by the pre-driver circuit, both transistors
200
,
210
have to be turned off. Turning off the PMOS transistor
200
also avoids current flow from the pad
212
to VDDIO. The PMOS transistor is ideally turned off by tying the gate of PMOS
200
high relative to the high voltage node. However, when the pad voltage exceeds VDDIO by VTP, the PMOS will not shut off. The NMOS transistor, in turn, is turned off by applying a low voltage such as VSSIO to the gate of NMOS
210
relative to the drain.
In the circuit of
FIG. 2
, during 5V tolerant mode, when the gate of PMOS
200
is at VDDIO (i.e. about 3.3 V for 5V tolerant mode) the drain to gate voltage is 2.2 V and is thus less than the oxide breakdown voltage, which is about 3.8 V. However, this does not turn off transistor
200
. The forward biased internal parasitic diode (indicated by reference numeral
216
) allows current flow of the order of milliamps. This results in heating of the cell and possible damage. In back-drive mode, when VDDIO is 0 V, the situation is even worse. The voltage to the source and gate of PMOS
200
is 0 V. This not only turns the transistor
200
on but also provides a voltage drop of 5.5 V across the drain-source junction and gate oxide which can cause irreparable damage.
One proposed prior art solution to reduce the gate oxide and drain-source junction voltages of the driver pull-up and pull-down transistors is to use cascoded p-channel pull-up transistors and cascoded n-channel pull-down transistors in the driver circuit, as shown in
FIG. 3
, in order to split the voltage across two pull-up and two pull-down transistors. The operation remains the same as for the simple circuit of
FIG. 2
, since one of the transistors in each cascoded pair is always kept on in normal mode, and the other transistor in each cascoded pair performs the toggling function to accommodate the load on the pad. Thus transistors
300
and
312
are always on during normal mode. It will be noted that even with NMOS transistor
300
asserted, current is prevented from flowing through the NMOS transistors
300
,
302
by grounding the gate of transistor
302
, which switches transistor
302
off.
However, the need for cascoded transistors results in more IC space being taken. The mobility of carriers in NMOS devices is approximately twice that in PMOS devices. Therefore, in order to maintain similar charge and discharge times for the PMOS pull-up and NMOS pull-down transistors, the PMOS device typically has to be twice the size of the NMOS device. By cascoding the devices, the transistors effectively present series resistances. In order to reduce this resistance effect, the size of the NMOS and PMOS devices is doubled. This provides NMOS devices that are each 2× the size of non-cascoded NMOS devices and PMOS devices that are each 4× the size of non-cascoded NMOS devices. Thus, the solution is costly to implement.
Furthermore, although the cascoding of the transistors splits the voltage, additional circuit elements still need to be introduced to avoid gate oxide breakdown and junction breakdown of the PMOS driver transistors, as well as current to VDDIO and well charging during stress mode. Also, the circuit of
FIG. 3
is for protection during 5V tolerant mode. In back-drive mode, since there is no supply voltage, the gate voltages of the driver output transistors are prone to gate oxide damage. Also, to avoid current flow through PMOS transistor
312
, the gate of PMOS
312
is charged to the same voltage as its drain. In order to prevent parasitic diode w
Lam Tuan T.
National Semiconductor Corp.
Nguyen Hiep
Vollrath Jurgen
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