Back biased CMOS device with means for eliminating latchup

Details Back biased CMOS device with means for eliminating latchup Back biased CMOS device with means for eliminating latchup

1985-02-12

1987-03-03

Wojciechowicz, Edward J.

357 48, 357 52, H01L 2702

Patent

active

046479562

ABSTRACT:
A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.

REFERENCES:
patent: 4300061 (1981-11-01), Mihalich et al.
patent: 4458262 (1984-07-01), Chao
patent: 4476476 (1984-10-01), Yu et al.
patent: 4480196 (1984-10-01), Hinz et al.
patent: 4490629 (1984-12-01), Barlow et al.
patent: 4513309 (1985-04-01), Cricchi
patent: 4559548 (1985-12-01), Iizuka et al.

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