Back bias voltage level detector

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327535, G05F 110

Patent

active

058865675

ABSTRACT:
A back bias voltage level detector includes a reference voltage generator outputting a reference voltage having a constant voltage, a PMOS pull-up transistor coupled to the reference voltage generator and an external voltage and outputting a gate-source voltage of the PMOS pull-up transistor, an NMOS pull-down transistor coupled to the PMOS pull-up transistor and a back bias voltage and outputting a gate-source voltage of the NMOS pull-down transistor, a couple of inverters connected in series between the PMOS pull-up transistor and the NMOS pull-down transistor and outputting an oscillation enable signal, and a couple of resistors connected in series between the back bias voltage and a ground voltage and connected to the NMOS pull-down transistor.

REFERENCES:
patent: 5013935 (1991-05-01), Mahabadi
patent: 5268595 (1993-12-01), Ohshima
patent: 5394026 (1995-02-01), Yu et al.
patent: 5757225 (1998-05-01), Tobita
Roubik Gregorian, Analog MOS Integrated Circuits for Signal Processing, 1986, p. 127.

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