B-ISDN sequencer chip device

Details B-ISDN sequencer chip device B-ISDN sequencer chip device

1992-06-04

1994-05-17

Evans, Arthur G.

Multiplex communications

Wide area network

Packet switching

370 60, 370 941, G06F 1300

Patent

active

053135792

ABSTRACT:
A sequencer chip device, provided for use in a broadband integrated service digital network (B-ISDN), is particularly adapted to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node surface interface (NNI) by a queue manager. The traffic enforcer contains a buffer to delay and reshape violating cells that do not comply with some agreed-upon traffic parameters. The queue manager manages cells in a queue at network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Proposed architectures for the traffic enforcer and the queue manager include the chip device. The chip device includes a plurality of modules each of which is divided into three main functional areas: controller, memory and comparator. The chip device is preferably implemented using 1.2 .mu.m CMOS technology.

REFERENCES:
patent: 5166926 (1992-11-01), Cisneros et al.
patent: 5197021 (1993-03-01), Cucchi et al.
L. Zhang, "VirtualClock: A new traffic control algorithm for packet switching networks," in Proc. SIGCOMM '90, Philadelphia, Pa. Sep. 1990, pp. 19-29.
J. S. Turner, "New directions in communications (or which way to the information age?)" IEEE Commun. Mag., vol. 24, No. 10, pp. 8-15, Oct. 1986.

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