Average bubble correction circuit

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S155000

Reexamination Certificate

active

06633250

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to the average bubble correction circuit in the analog to digital converter. The average bubble correction circuit can convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.
(b) Description of the Prior Arts
In the deep submicron technology, the channel length will be shorter and the breakdown voltage will be decreased when the device is made smaller. Therefore, in order to improve the reliability of the circuit and to obtain the better yield of the product, the working voltage has to be decreased to a certain value. The device whose channel length (&lgr;) is 3.5 micrometers can take the working voltage 3.3 V. However, when the channel length (&lgr;) of the device is decreased to 2.5 micrometers, the working voltage 3.3 V will cause the problem of reliability. The working voltage has to be decreased to 2.5 V accordingly to maintain the reliability when the channel length is changed to 2.5 micrometers. In general, the working voltage needs to be decreased as the manufacturing process advanced. It is the nature in physics that the decrease of the working voltage is proportional to the decrease of the channel length. Example that when the channel length (&lgr;) decreasing from 3.5 micrometers to 2.5 micrometers, the working voltage has to be decreased from 3.3 V to 2.5 V. Another factor is the threshold voltage that affects the working voltage, the threshold voltage is not changing in proportion with the change of the channel length (&lgr;) accordingly. For example, when the channel length (&lgr;) changing from 3.5 micrometers to 2.5 micrometers (the ratio is 0.09), the threshold voltage will change from 0.7 V to 0.56 V (the ratio is 0.8), which means, for a designer of a circuit, the linear voltage range is decreased, for example, from 1.5V to 1 V.
The main disadvantages of the analog to digital converter are as follows: (1) signal range (2) resolution (N bits) (3) random offset voltage of the device. The least significant bit voltage V
LSB
can be represented as V
LSB
=V
&eegr;
/2
N
when the signal range is V
&eegr;
and the resolution is N bits.
The practical circuit has to resolute a least significant bit voltage V
LSB
(strictly, to ½V
LSB
) in order to meet the demand of the N-bit analog to digital converter. From the formula above, the least significant bit voltage V
LSB
is proportional to the signal range V
&eegr;
and the signal range V
&eegr;
has to be in the linear voltage range. In advanced manufacturing process, the signal range V
&eegr;
and the least significant bit voltage V
LSB
will be decreased when the working voltage decreased.
The random offset voltage V
os
of MOS and the thermal noise V
n
are the bottlenecks of decreasing the least significant bit voltage V
LSB
. Any circuit will not detect the degree of the signal when the least significant bit voltage is smaller than the thermal noise or is smaller than the random offset voltage. With the auto correction circuit or the offset calibration circuit, the better resolution can be obtained. Example that the signal range is 1.5 V when the working voltage is 3.3 V in the process whose channel length is 3.5 micrometers, the least significant bit voltage of the 8-bit analog to digital converter is equal to 5.86 mV and the random offset voltage is between 10 mV and 20 mV, obviously, the V
LSB
is much smaller then the V
os.
Therefore, the probability of the generating of the bubble will increase for the flash analog to digital converter. And, vary likely; several bubbles will be generated in the same time.
The effects of the bubbles are as follows: (1) the error of the decoding of read only memory (ROM) (2) the decreasing of the rate of the noise of the signal (3) the increasing of the bit error rate. When the bubbles are more than one, the number of the inputs of the decoder which is preset will be more than one “1” and will not be corrected, and further result in the error of the binary code of the outputs. And the current passing through the transistor will increase extremely and the bit error rate will cause the data sampling fail to meet the specification. The yield will not be improved and the cost will increase. So, the better error correction circuit is vary important for the analog to digital converter in the advanced manufacturing process.
FIG. 1
is showing the schematics of the flash analog to digital converter in prior art. The output of the comparator
12
in the flash analog to digital converter
10
is the thermometer code. If the input voltage of the comparator is higher than the reference voltage, the logical output is “1”. If lower, the logical output will be “0”. The analog signal converted to the digital signal is shown in FIG.
2
. The analog signal outputted from a series of the comparators
12
will be similar to the thermometer code style in FIG.
2
. In order to form the thermometer code style, all “0” will be above the input voltage and all “1” will be under the input voltage. The boundary of the “1” and “0” can reflect the degree of the input voltage. The thermometer code will be converted to 1-OF-N code by 1/0 state-conversion detector and will be decoded to binary code by ROM
14
.
Because of (1) high slew rate input (2) the difference of the clock pulse distribution (3) process offset, the micro difference of the random input offset voltage and the response time of the comparators will result in one or many “0”s appear in a series of “1”, or one or many “1”s appear in a series of “0”, and this is so called bubble error.
When the errors happened in the analog to digital converter, two or more 1/0 state-conversion points will appear, and which will cause errors occur in the process of decoding and further cause the increasing of the bit error rate and the decreasing of the noise signal rate of the analog to digital converter. The problem of the error code of the bubble can be solved by using three-end input logical device that referring three continuous thermometer codes.
FIG. 3A
is showing the diagram of the three-end input logical device which can detect the 1/0 state-conversion point with input “001”. When the thermometer codes that input to the AND gate
30
of the three-end logical input device is “001” and the output signal of the AND gate
30
is “1”, it is indicating that the 1/0 state-conversion point has been detected, otherwise, the output signal of the AND gate
30
is “0”.
FIG. 3B
is showing the diagram of the three-end input logical device which can detect the 1/0 state-conversion point with input “011”. When the thermometer codes that input to the AND gate
32
of the three-end logical input device is “011” and the output signal of the AND gate
32
is “1”, it is indicating that the 1/0 state-conversion point has been detected, otherwise, the output signal of the AND gate
30
is “0”.
The thermometer codes will be converted to 1-OF-N codes by using the three-end logical input device and will be further decoded into the binary codes.
FIG. 4
is showing the condition that the bubble being detected by the three-end logical input device in prior art. The disadvantage of the three-end logical input device is that the 1/0 state-conversion point can be detected, but the result is not the best one. For example, in
FIG. 4
, the three-end logical input device will use “011” or “001” to detect the 1/0 state-conversion point, and the result is showing in the (a) series and (b) series thermometer codes in FIG.
4
. When the thermometer codes of the comparator
40
and the comparator
42
generate the bubbles, the three-end logical input device will not detect which comparator generating the errors. As shown in
FIG. 4
, the 1/0 state-conversion points that detected by the (a) series and the (b) series thermometer codes are not the proper ones, however, the (c) series thermometer codes will generate the best result.
FIG.
5
B and
FIG. 5C
are showing the several kinds of results that the three-end logical

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