Avalanche stress protected semiconductor device having variable

Details Avalanche stress protected semiconductor device having variable Avalanche stress protected semiconductor device having variable

1991-01-07

1992-05-19

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

361 57, 323289, 307570, H02H 902, H03K 1708, G05F 163

Patent

active

051153696

ABSTRACT:
A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

REFERENCES:
patent: 3947727 (1976-03-01), Stewart
patent: 4845420 (1989-07-01), Oshizawa et al.
patent: 4893158 (1990-01-01), Mihara et al.
patent: 4950930 (1990-08-01), Patni
patent: 4993396 (1991-02-01), Miura

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