Auxiliary control signal decode using high performance address l

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364DIG1, 3642403, 36496577, G06F 1314, G06F 1318

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active

054230217

ABSTRACT:
An apparatus that develops the M16* control signal, which indicates a 16 bit memory device is responding, from the latched address LA<> lines to provide a faster response time than if it were decoded from the SA<> address lines. Decode values for specific 8 kbyte blocks in a 128 kbyte address range are stored. The particular value for an 8 kbyte block is multiplexed and provided to the M16* line based on the decode of the LA address lines.

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