Autozeroed set comparator circuitry

Details Autozeroed set comparator circuitry Autozeroed set comparator circuitry

1989-06-19

1991-01-29

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

307362, H03K 5153

Patent

active

049890034

ABSTRACT:
A comparator circuit for operation at video rate signals includes input switches to alternately couple a reference and a signal potential to a summing capacitor. The capacitor is coupled to the input of a first inverting amplifier. The amplifier includes a switch between input and output terminals for selectively autozeroing the amplifier. The amplifier is direct coupled to the input of a second inverting amplifier having an autozero circuit exclusive of a connection to the input of the second amplifier. Timing circuitry for controlling the autozero function is arranged to minimize the effects of clocking transients upsetting the autozeroed potentials thereby reducing the response time and enhancing the sensitivity of the comparator.

REFERENCES:
patent: 4262221 (1981-04-01), Dingwall
patent: 4532438 (1985-07-01), Reiner
patent: 4535257 (1985-08-01), Hareyama
patent: 4547683 (1985-10-01), Bingham
patent: 4598215 (1986-07-01), Schechtman et al.
patent: 4667180 (1987-05-01), Robinson
patent: 4691189 (1987-09-01), Dingwall
patent: 4845383 (1989-07-01), Iida
Sn. 137,230, filed 12/23/87 by D. J. Sauer entitled "A Switched Capacitor Arrangement".
Sn. 07/329,162 filed 03/27/89 by D. J. Sauer entitled "Comparator Circuitry".
Yee et al., "A 1 mu MOS Comparator", IEEE Journal of Solid State Circuits, vol. SC-13, No. 3, Jun. 1978, p. 294.
IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 86, "High Speed, High Sensitivity Comparator".

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