Communications: directive radio wave systems and devices (e.g. – Directive – Including a satellite
Reexamination Certificate
1999-09-17
2001-08-21
Tarcza, Thomas H. (Department: 3662)
Communications: directive radio wave systems and devices (e.g.,
Directive
Including a satellite
C375S344000, C701S213000
Reexamination Certificate
active
06278403
ABSTRACT:
FIELD OF INVENTION
This invention relates to the field of GPS receivers.
BACKGROUND OF INVENTION
The Global Positioning System is a navigation system that can be used to provide a user with accurate position and time. It consists of a constellation of GPS satellites that broadcast the GPS signal, ground stations to control those satellites, and radio receivers such as shown in
FIGS. 1A and 1B
to capture the GPS signals and extract navigation information from them. Encoded on the transmissions of each satellite are messages that indicate the location of the satellite and time of transmission of the signal. By acquiring the signal of four satellites, and by performing calculations to determine the difference between the time of transmission and time of reception by the user equipment, a user can triangulate and determine latitude, longitude, elevation, and time. As illustrated in both prior art radio receiver implementations of
FIGS. 1A and 1B
, a typical GPS radio receiver comprises an antenna
12
up front to capture a GPS signal
13
broadcasted from a satellite. A RF front end
14
uses a reference oscillator
16
to down convert input RF signal
13
to an analog IF signal
15
. An analog to digital converter (A/D)
18
samples analog IF signal
15
and converts it into a digital IF output
19
. IF signal
19
then undergoes digital signal processing comprising essentially three levels of signal processing illustrated in Table 1 below.
TABLE 1
Receiver Functionality vs. Processing Rate Frequency
FUNCTIONALITY
Signal Sampling &
Navigation & Other
Correlation (i.e.,
Receiver Processing
Processing (i.e.,
correlation,
(i.e., Tracking Loops,
Calculations of
replicating P or C/A
Bit Synchronization,
Position & Time,
code)
Data Demod, etc.)
User Applications)
Processing
High rates
Medium rates
Low rates
Frequency
(i.e.,50 MHz to 1 KHz)
(i.e., 1 KHz to 10 Hz)
(i.e., 10 Hz and
slower)
FIG 1A
ASIC (i.e., Correlator
CPU #1 (i.e., CPU 22) performs receiver
Prior Art
20) performs process
processing, navigation & other processing
Scheme
(interrupted at medium rate)
FIG. 1B
ASIC (i.e., Correlator
CPU #1 (i.e., CPU 22)
CPU #2 (i.e., CPU
Prior Art
20) performs process
performs receiver
26) navigation &
Scheme
processing (interrupt at
other processing
medium rate)
(interrupt at low rate)
The three levels of signal processing can be quantified according to the functions and processing frequency expected at each stage of processing. A first stage consists of signal sampling and correlation processing that is CPU intensive and operates at very high frequency processing rate such as typically between 1 KHz to 50 MHz processing rate. This correlation processing stage comprises processing various steps that compare (or correlate) digitized signal
19
with a locally generated code that attempts to replicate the P or C/A code generated by a satellite. The replica code searches a “space” that consists of the unique codes generated by the different satellites, the temporal portion of the code being sent at any given time, and the Doppler frequency offset caused by the relative motion of the satellite and user. Generally, the Correlator Engine (such as Correlator
20
of
FIGS. 1A and 1B
) performs parallel correlations with multiple code position/Doppler value combinations simultaneously in a multiple channel fashion, usually up to 12.
A second stage shown in Table 1, referred to as the receiver processing, typically comprises performing tracking loop function, bit synchronization, data demodulation, and other such typical signal processes running at a medium rate of 1 KHz to 10 Hz signal processing rate requirement. Finally, a third stage of signal processing illustrated in Table 1 comprises low frequency rate signal processing of 10 Hz or slower processes typically found in navigation processing, such as calculation of position and time.
As summarized in Table 1, typical prior art implementation of
FIG. 1A
provides that the high rate signal sampling and correlation functions are performed by a Correlator ASIC
20
, while all other remaining medium to low level processing is performed by a receiver CPU
22
. This implementation presents a substantial drawback in that the receiver CPU
22
is overly burden with the still intensive processing requirements expected of the typical receiver processing function (i.e., 1 KHz to 10 Hz rate processing) that competes with the navigation processing and other non-GPS applications, including user applications. Moreover, as also summarized in Table 1, prior art implementation of
FIG. 1B
of providing two CPUs (a receiver CPU
22
and a navigation process CPU
26
) to segregate and offload the medium frequency rate processes from the navigation CPU thus provides more time for that CPU to allocate to other non-GPS processing. However, prior art scheme of having a second CPU results in substantial increase to cost and silicon.
Accordingly, for typical radio receiver applications, either a more powerful CPU (with increased power consumption) needs to be used, or user desired software applications suffer from the microprocessor limited bandwidth to service both the correlator engine operations as well as the typical GPS receiver and navigational processing. There is therefore a dire need to off load the functions of the microprocessor in a GPS receiver system, while still servicing the needs of correlator engine operations and maintain the GPS receiver system performance.
SUMMARY OF INVENTION
An autonomous Hardwire Tracking Loop (HWTL) radio receiver comprising a CPU, a Correlator Engine (a “Correlator”) and a Hardwired Tracking Loop (“HWTL”) coprocessor is provided in accordance with the principles of this invention. The HWTL coprocessor provided in a HWTL integrated circuit executes acquisition and tracking procedures in radio receivers, such as a GPS and WAAS receiver that have traditionally been executed in software by the CPU. Accordingly, providing a HWTL coprocessor frees up the CPU to perform various other critical navigational and user desired applications, while minimizing the cost and real estate required. In the preferred embodiment, the Correlator Engine, the HWTL coprocessor, and the CPU are all integrated on a single integrated circuit to minimize power consumption and lowers cost and also to relax the GPS receiver system's CPU requirements to allow the CPU more bandwidth to address user applications and lower CPU frequency intensive signal processing that are 10 Hz or less.
The receiver processing functions performed by the HWTL coprocessor include typical acquisition and tracking functions such as, for example, carrier loops, code loops, code lock detect, costas lock detect, bit synchronization, data demodulation, and SNR data gathering. The HWTL coprocessor implements the search processing for initial acquisition or reacquisition to track as well as controlling exit processing of track to reacquisition, as determined by CPU programmable parameters. The HWTL coprocessor can operate on a single channel in initial acquisition or on up to twelve channels in reacquisition or track. If the HWTL coprocessor is operating in reacquisition/track mode, then one of the channels may be a WAAS channel.
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Falk Henry D.
Marumo Wesley F.
Peng Leon Kuo-Liang
Gates & Cooper LLP
Mull Fred H
SiRF Technology Inc.
Tarcza Thomas H.
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