Automating photolithography in the fabrication of integrated cir

Details Automating photolithography in the fabrication of integrated cir Automating photolithography in the fabrication of integrated cir

1995-08-08

1997-09-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

With measuring or testing

36446828, 364490, H01L 2166

Patent

active

056630760

ABSTRACT:
Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

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patent: 4948458 (1990-08-01), Ogle
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patent: 5498579 (1996-03-01), Borodovsky et al.
J.B. Carter et al, "Transformer Coupled Plasma Etch Technology for the Fabrication of Sub-half Micron Structures," 1992.

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