Automatically calibrated phase locked loop system and...

Details Automatically calibrated phase locked loop system and... Automatically calibrated phase locked loop system and...

2002-06-18

2004-11-09

Nguyen, Minh (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C327S156000

Reexamination Certificate

active

06816019

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of automatically calibrating a phase locked loop (PLL) system, and to a PLL system comprising at least one phase detector cascade connected to a low-pass filter and to a controlled oscillator, as well as to a frequency divider that is feedback connected between the controlled oscillator and the phase detector. The invention relates particularly, but not exclusively, to a method of automatically calibrating a PLL system specifically providing a frequency multiplier function.
BACKGROUND OF THE INVENTION
A phase locked loop or PLL system, diagrammatically shown in
FIG. 1
, comprises a phase detector PD, a low-pass filter LPF, and a voltage-controlled oscillator VCO cascade connected together between an input terminal IN and an output terminal OUT of the PLL system.
A conventional PLL system also includes a frequency divider DIV, which is feedback connected between the output terminal OUT and the input terminal IN. In particular, the phase detector PD detects a phase difference between first S
REF
and second S
VCO
input signals.
The first input signal S
REF
is an oscillating signal at a reference frequency F
REF
, and the second input signal S
VCO
is an oscillating signal at a feedback frequency F
VCO
that is derived from an oscillation output frequency F
OUT
of an output signal S
OUT
from the controlled oscillator VCO, as suitably divided within the frequency divider DIV. Since a PLL system operates according to the oscillation frequencies of the signals that flow through it, reference will hereinafter be made to frequencies of interest. These frequencies are the oscillation frequencies of corresponding oscillating signals.
The PLL system shown in
FIG. 1
further includes a charge pump phase comparator CPPC connected between the phase detector PD and the low-pass filter LPF. In particular, the charge pump phase comparator CPPC allows a charge stored in a capacitor, provided in the low-pass filter LPF, to be injected, removed, or left unchanged as may be controlled by first UP and second DOWN output signals from the phase detector PD. These output signals UP and DOWN have pulses that are related to the amount of shift that exists between the input frequencies F
REF
and F
VCO
to the phase detector PD, as diagrammatically shown in FIG.
2
.
The low-pass filter LPF is used to extract an average value from an output voltage signal V
LPF
from the charge pump phase comparator CPPC. This is done so that a voltage signal V
VCO
can be input to the controlled oscillator VCO and a desired frequency can be obtained.
To further clarify operation of the PLL system, reference will now be made to
FIG. 3
, which shows a portion of the PLL system of
FIG. 1
in greater detail. In particular,
FIG. 3
shows a circuit structure
1
, which corresponds to a combination of the charge pump phase comparator CPPC, the low-pass filter LPF, and the controlled oscillator VCO in the PLL system of FIG.
1
.
The circuit structure
1
comprises an operational amplifier
2
having a first input terminal IN
1
connected to a first internal circuit node X
1
of the circuit structure
1
. This node is connected to a supply voltage reference Vcc through a control resistive element R
VCO
. A second input terminal IN
2
is connected to a second internal circuit node X
2
. More specifically, this node is intermediate first G
1
and second G
2
generators supplying a reference current Iref. These generators are connected in series with each other between the supply voltage reference Vcc and a second voltage reference. The second voltage reference is specifically a ground reference GND. The circuit structure
1
further includes an output terminal OUT
1
connected to a control terminal of an output transistor M
OUT
. The output transistor M
OUT
is connected between the first internal circuit node X
1
and the controlled oscillator VCO.
The first and second generators G
1
and G
2
are connected to the second internal circuit node X
2
through first SW
1
and second SW
2
electronic switches that are respectively driven by the output signals UP and DOWN from the phase detector PD. The output transistor M
OUT
drives the controlled oscillator VCO by supplying it with a regulating current I
VCO
.
The circuit structure
1
additionally comprises a first filtering capacitor Cf
1
and a filtering resistive element Rf, which are connected in series with each other, between the second input terminal IN
2
of the operational amplifier
2
and ground GND. A second filtering capacitor Cf
2
is connected to a point intermediate the first filtering capacitor Cf
1
and the filtering resistive element Rf, as well as to ground GND.
The size of the low-pass filter LPF is set by adjustment of the values of the first and second capacitors Cf
1
and Cf
2
, and the value of the filtering resistive element Rf. In particular, to obtain a damping factor (which is one of the characterizing parameters of a system dynamic response) such that the transient of the PLL system can be fast and does not show any overshoots, filter elements can be used that have the following values: Cf
1
=1 nF; Rf=76 k&OHgr;; and Cf
2
=200 pF.
In this way, a damping factor of approximately 0.7 is obtained. This is regarded as an optimum value for closed-loop systems. Because of its size, the first filtering capacitor Cf
1
cannot be integrated to the remainder of the PLL system, and is provided externally. The second filtering capacitor Cf
2
reduces spikes in the control voltage V
LPF
waveform at the second internal circuit node X
2
. The spikes originate from switching of the switches SW
1
and SW
2
.
The output voltage V
VCO
from the low-pass filter LPF controls the regulating current I
VCO
to the controlled oscillator VCO. This is done through the regulating resistive element R
VCO
connected between the supply voltage reference Vcc and the first internal circuit node X
1
.
It is readily known that a voltage controlled oscillator VCO can be formed by a series of variable-current inverters connected into a loop and having capacitors interposed therebetween. The VCO outputs a signal S
OUT
whose oscillation frequency F
OUT
is tied to the input current I
VCO
.
The operation of the subject PLL system will be better explained by considering the illustrative case of a pulse in the first output signal UP received at a given time from the phase detector PD. This implies that the feedback frequency F
VCO
from the frequency divider DIV is late on the reference frequency F
REF
. In this case, the charge pump phase comparator CPPC will respond by closing the second switch SW
2
to ground GND. This causes the charge stored in the first filtering capacitor Cf
1
to be diminished.
In this way, an increase in the input current I
VCO
to the controlled oscillator VCO is obtained, which produces an increase in the output frequency F
OUT
, and accordingly, brings the feedback frequency F
VCO
back into phase with the reference frequency F
REF
. The frequency divider DIV in the feedback leg turns the PLL system into a frequency multiplier by a multiplication factor N. In several applications, e.g., hard-disk noise compensation using an accelerometer and feed-forward compensation techniques, the multiplication factor N to be used is fairly large, and the operating frequency range that is possible for the PLL system becomes wide.
By way of example and not to be a limitation, in case of a hard-disk control, the frequency values and multiplication factors may be: F
REF
: 5 to 30 kHz; and F
CVO
: 1.12 to 6.72 MHz with N=224. Setting such values makes for more complicated sizing of the PLL system components. In particular, to obtain all the desired frequencies, the input current I
VCO
to the controlled oscillator VCO is forced to values that are incompatible with the current values through the remainder of the PLL system.
It can be shown that the following relation applies to a PLL system like that illustrated by FIGS.
1
and
3
:
F
VCO
F
REF
=
(
1
+
sRfCf
⁢
 
⁢
1
)
1

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