Automatic wiring method for semiconductor integrated circuit dev

Details Automatic wiring method for semiconductor integrated circuit dev Automatic wiring method for semiconductor integrated circuit dev

1991-02-27

1992-06-23

Thomas, Tom

Fishing, trapping, and vermin destroying

357 45, 364491, H01L 2170, G06F 1560

Patent

active

051242737

ABSTRACT:
A computer-assisted automatic wiring method is presented for logic LSI substrates wherein channel boundary terminals are defined on the boundary line of the first and second channels forming a T-shaped crossing region between the function blocks arranged on a substrate after global wiring process. These channel boundary terminals are roughly divided into the first and second terminal groups there may remain channel boundary terminals which do not belong to any one of the groups. The first terminal group includes terminals intersecting wirings which tend to run along the first direction in the second channel, which corresponds to a top bar of the letter "T". The second terminal group includes terminals intersecting wirings which have tend to run along the second direction opposite to the first direction in said second channel. A pair of channel boundary terminals is sequentially selected from the first and second groups. Typically, the same wiring track is assigned to two wirings associated with the selected each pair of terminals in the second channel.

REFERENCES:
patent: 4636965 (1987-01-01), Smith et al.
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4823278 (1989-04-01), Kikuchi
patent: 4839820 (1989-06-01), Kinoshita
patent: 4839821 (1989-06-01), Muralcata
patent: 4910680 (1990-03-01), Hiwatashi
patent: 4965739 (1990-10-01), Ng
1982 IEEE, "Optimum Placement of Two Rectangular Blocks", M. Chandrasekhar and M. Breuer, 19th Design Automation Conference, Paper 46.6, pps. 879-886.

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