Automatic verification of external interrupts

Details Automatic verification of external interrupts Automatic verification of external interrupts

1994-12-20

1997-01-07

Harvey, Jack B.

Excavating

371 27, 395500, G06F 9455, G06F 946

Patent

active

055926746

ABSTRACT:
A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method allows the verification of the architectural aspects to the external interrupt mechanism in pipelined and super scalar microprocessors. The method which is based on the assumption that when an external interrupt is serviced, the processor branches to a specific address according to the type of the external interrupt. The first step in the method is a preparation step wherein the memory addresses already used by the test are scanned and unused memory spaces are allocated for a plurality of memory blocks and two memory addresses for pointers. These two addresses are used to find the next block to fill. After this initial preparation step, the interrupt is presented in any desired location by the design simulator controller. Next, the instruction range in which the external interrupt could be serviced is found. External interrupt routines are added to the test. These routines are executed each time the appropriate external interrupt is served by the processor. Finally, the reference model of the processor is used to recompute the expected results of the test. In this process, each external interrupt will update its unique block of memory and, as a result, if the processor sets any of these resources to an incorrect value while servicing any of the external interrupts presented in the test, it will be detected as the actual results of the test will be different than those expected in the test program. A mask is used to detect latency violations. The value saved in memory is independent of the actual timing of the interrupt since all the unknown bits are reset by the mask. By using an offset, the chances of detection of a latency violation are improved.

REFERENCES:
patent: 4636941 (1987-01-01), Suko
patent: 4891773 (1990-01-01), Ooe et al.
patent: 4899306 (1990-02-01), Greer
patent: 5193195 (1993-03-01), Miyazaki
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5247628 (1993-09-01), Grohoski
patent: 5301312 (1994-04-01), Christopher, Jr. et al.
patent: 5313468 (1994-05-01), Hoshi et al.

Affiliated with

Also associated with

Rating

Automatic verification of external interrupts does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic verification of external interrupts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic verification of external interrupts will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1773725