Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-11-18
2001-02-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S323000, C327S063000, C327S065000, C327S067000
Reexamination Certificate
active
06188264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic threshold level control circuit, which automatically changes an threshold level of an input signal in response to the dynamic change of the power level of the input signals.
2. Background Art
Conventionally, an automatic threshold level control circuit for automatically controlling the threshold level in response to the dynamic changes of the power level has been used in a receiver in a burst digital light signal transmission system such as full service access network transmission system. One example of this type of automatic threshold level control circuit is disclosed in Japanese Patent Application, First Publication No. Hei 10-126349 entitled “Burst Light Receiving Circuit”.
FIG. 6
is a circuit diagram showing an example of a feed-forward-type conventional automatic threshold level control circuit for determining the threshold level in response to the input signal. In the feed-forward-type ATC (Automatic Threshold Level Control) circuit
600
shown in
FIG. 6
, two pulse signals, in which amplitudes of respective pulse signals switch between normal phase or negative phase, are input into terminals ATCIN+ and ATCIN−, respectively. The input terminal ATCIN+ is connected to a peak value detecting circuit PD2 (
64
) and a resistor
1
, and the input terminal ATCIN− is connected to a peak value detecting circuit PD1 (
62
) and a resistor
3
. The peak value detecting circuit PD1 (
62
) holds the peak level of the input signal in a capacitor C
pd1
and outputs the peak level. The peak value detecting circuit PD2 (
64
) resets the charged voltage of the capacitor C
pd1
to the reference voltage V
ref1
by turning on a MOS (Metal Oxide Semiconductor) transistor
63
connected to the capacitor C
pd1
, when the reset signals input to a terminal RST changes high level. Similarly, the peak value detecting circuit PD2 (
64
) holds the peak level of the input signal and outputs it. When the reset signals input to a terminal RST changes high level, the MOS transistor
65
connected to the capacitor C
pd2
is turned on and the voltage of the capacitor C
pd2
is reset.
Here, a buffer amplifier
61
connected to the feed-forward-type ATC circuit
600
outputs to the positive phase output terminal ATCOUT+ a voltage amplified after dividing the input voltage in the input terminal ATCIN+ and the output voltage V
PD1
by the resistor R
1
and the resistor R
2
connected in series with the output of the peak value detecting circuit PD1 (
62
). The buffer amplifier
6
also outputs to the negative phase output terminal ATCOUT− a voltage amplified after dividing the input voltage to the input terminal ATCIN− and an output voltage V
PD2
of the peak value detecting circuit PD2 (
64
).
FIG. 7
is a waveform diagram showing time dependent changes of operating voltages of each portion of the feed-forward-type ATC circuit
600
shown in FIG.
6
and an output voltage of the buffer amplifier
61
. For the circuit shown in
FIG. 6
, the same reset signals RST are input into both the peak value detecting circuit PD1 (
62
) and PD2 (
64
) in the guard time between the burst signals. Consequently, in an example shown in
FIG. 7
, since the peak detecting circuit PD1 (
62
) holds the level where there are no signals, a DUTY ratio degradation will be caused which corresponds to the change of the duty ratio of the output pulse signal from that of the input signal when the level of the input signal “0” differs from that of no signal level.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an automatic threshold level control circuit, which is capable of controlling the threshold level of input signals without causing the DUTY deterioration.
According to the first aspect of the present invention, the automatic threshold level control circuit comprising: a pair of peak value detecting circuits for preserving the peak voltage values of each input signal for input signals changing in a mutually negative phase to each other, for outputting the held voltage value as the standard for the threshold level of each input signal, and for resetting the preserving voltage value to the predetermined reference voltage value by a reset signal; and a timing detecting circuit for detecting a timing according to the change of the input signal and for outputting the reset signal for releasing the reset state corresponding to the detected timing to said peak value detecting circuit.
According to the second aspect of the present invention, in the automatic threshold level control circuit, the timing detecting circuit outputs a reset signal for releasing the reset state in response to the timing when the input signal level changes.
According to the third aspect, in the automatic threshold level control circuit, the timing detecting circuit outputs a pair of reset signals for releasing the reset state to each peak value detecting circuit independently in response to the change of the edge of each input digital signal.
According to the fourth aspect, in the automatic threshold level control circuit, the timing detecting circuit comprises a comparator which operates by inputting an input signal and at least a pair of RS flip-flop circuits which operate according to the output of the comparator, and said timing detecting circuit detects a predetermined timing in response to the change of the input signal, temporarily holds the reset signal to be output by the RS flip-flop circuit, and releases the reset state by the output of the comparator. According to the above described structure, an automatic threshold level control circuit is provided which has a simple structure and which is suitable for high speed processing.
REFERENCES:
patent: 5028815 (1991-07-01), Van De Plassche
patent: 5307196 (1994-04-01), Kinoshita
patent: 5712581 (1998-01-01), Kaylor
patent: 6041084 (2000-03-01), Nagaraj
patent: 8-293838 (1996-11-01), None
patent: 9-181687 (1997-07-01), None
patent: 10-126349 (1998-05-01), None
patent: 10-210088 (1998-08-01), None
Kakinoki Akira
Masuta Tomoaki
Callahan Timothy P.
Luu An T.
NEC Corporation
Young & Thompson
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