Automatic test system having a "true tester-per-pin" architectur

Details Automatic test system having a "true tester-per-pin" architectur Automatic test system having a "true tester-per-pin" architectur

1988-12-22

1990-06-05

Eisenzopf, Reinhard J.

Excavating

324158R, 324 731, 371 251, 371 27, G01R 3128, G01F 1112

Patent

active

049317237

ABSTRACT:
A multichannel automatic test system for an electronic circuit utilizes a "true tester-per-pin" architecture; each channel of the tester operates as if it were an independent tester. Each channel of the tester has a memory circuit which stores instructions for operating that channel of the tester. Each of these memories is cycled to the next address to provide a new instruction for that channel, only when it is necessary to change the state of operation of that channel. Thus, the timing of the events on one channel are independent of the timing on the events of any other channel in the tester. The architecture permits the use of dynamic random access memory (DRAM) circuits and allows for backward looping in the test sequence through the use of a cache memory circuit in each channel. The instructions for operating each channel of the tester are context-dependent; that is, the present state of operation of that channel of the tester is utilized in interpreting the next instruction for that channel.

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