Automatic test process with non-volatile result table store

Details Automatic test process with non-volatile result table store Automatic test process with non-volatile result table store

1997-11-17

2000-07-11

Dutton, Brian

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438 18, H10L 2100, H10L 2166, G01R 3126

Patent

active

060871903

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to the manufacture and testing of integrated circuits; and more particularly to circuits to test integrated circuits such as EEPROMs or FLASH memory for production purposes.
2. Description of Related Art
In the manufacture of integrated circuits, testing for both engineering and production purposes is critical. Thus, most integrated circuits incorporate test circuitry on the chip to facilitate the testing processes. The ability to test a large number of devices at one time is particularly important for production purposes, where the testing step is incorporated into the method for manufacturing the integrated circuit. In production testing systems for "gangs" of integrated circuits, the amount of data which must be monitored by a processor controlling the testing can be quite large. This slows down the testing processes, and limits the amount of information which can be processed during the testing mode.
Testing is of significant importance in the non-volatile memory device field. For instance, the memory devices must be tested for endurance, and qualified according to read and write speed and threshold margin specifications during manufacturing. Also, the endurance, read and write speed and threshold parameters of the circuit are important for engineering purposes during the design of a product.
One popular class of non-volatile memory cell is based on a floating gate transistor which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons which causes the turn-on threshold of the memory cell to increase. Thus, when programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
Further, commercial designs include circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth.
Also, commercial devices incorporate automatic program and erase modes which can be used for testing the operation of the non-volatile design.
In order to meet specific quality requirements for floating gate memory devices like FLASH EPROMs and EEPROMs, program and erase cycling is required to screen out devices which have low endurance (i.e., suffer "infant mortality"). To simplify the hardware requirements for the testing and reduce the cycle time, gang cycling is required in the production environment. Thus, it would be desirable to provide an automatic program and erase mode with some intelligence to facilitate gang cycling. For engineering, it is also important to have a mode that will record the status of the device during cycling to indicate the endurance of the specific device.
Also during the manufacturing of the integrated circuits, the devices are characterized according to their performance characteristics such as voltage margins, endurance, speed of operation, and the like. Information about the group of integrated circuits being tested is processed by a testing machine in order to bin-out the devices having varying specifications. Thus, high speed devices can be sold at a higher price than low speed devices. Devices with greater voltage margins can be sold at higher prices than lower margin devices. Other results of testing, such as the detection of bad segments in the memory, and the like can be also used to bin-out devices.
Thus, during the testing a large amount of data is accumulated about the integrated circuits under test. As the number of circuits under test gets large in a given system, and the speed of testing is increased, all this information b

REFERENCES:
patent: 3659088 (1972-04-01), Boisvert, Jr.
patent: 5627838 (1997-05-01), Lin et al.

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