Automatic test insertion

Details Automatic test insertion Automatic test insertion

1996-04-10

1997-08-26

Canney, Vincent P.

Excavating

364489, G06F 1100

Patent

active

056617330

ABSTRACT:
A method of inserting automatic test logic into a synthesized logic circuit. The method operates in two phases using a synthesized netlist of the logic circuit as an input. The first phase uses outputs of a fault grading tool, and alters the netlist to incorporate fault grading logic additions such as flip-flops to provide control and observation points within the logic circuit and gate modifications dictated by the fault grading tool. The second phase adds scan structures to the synthesized logic circuit using parameters such as the number and length of scan chains determined by a user. Buffering associated with scan hook-up and scan mode lines is determined and distributed buffering is then added to the netlist to output a modified output netlist. The resultant synthesized logic circuit defined by the modified output netlist is functionally identical (when not in scan mode) to the original design, but has test insertion logic added to it, and thus includes a high fault grade percentage and scan logic functions.

REFERENCES:
patent: 5463562 (1995-10-01), Theobald
patent: 5513188 (1996-04-01), Parker et al.
patent: 5612891 (1997-03-01), Butts et al.

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