Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Phase comparison
Reexamination Certificate
2000-07-26
2001-09-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Phase comparison
C324S076470, C327S217000, C327S199000
Reexamination Certificate
active
06291981
ABSTRACT:
This invention relates generally to automatic test equipment and more specifically to the circuitry that allows automatic test equipment to generate stimulus signals with narrow pulse widths.
Automatic test equipment is widely used to test semiconductor components during their manufacture. The automatic test equipment generates stimulus signals and measures responses from a device under test. The responses are compared to the expected responses from a fully functioning chip to determine whether the device under test is fully functional.
The automatic test equipment is programmed with a pattern that represents the stimulus and expected data for a device under test. Different kinds of devices under test will require different patterns for testing. Thus, the automatic test equipment must be flexible enough to generate a wide range of signals that are compatible with the types of signals many types of chips generate or receive.
FIG. 1
shows a prior art test system in simplified block diagram form. The system includes a tester body
110
and a computer work station
112
that controls the operation of the tester body and provides a user interface.
Within tester body
110
, there are multiple copies of circuitry called a channel
114
. Each channel
114
, generates or measures a signal on one lead of a device under test. A channel
114
includes a pattern generator
120
, a timing generator
122
a failure processor
124
, a formatter
126
a driver
128
and a comparator
130
.
Pattern generator
120
stores the pattern that defines the data that is to be applied or is expected during each cycle of tester operation. The data specifies whether the tester is to drive data or measure data during that cycle. The pattern includes information specifying the data value, such as a logic 1 or a logic 0.
Additionally, the format of the signal must be specified. For example, some semiconductor devices represent a logical 1 by having a signal line at a high voltage during an entire cycle. Other chips represent a logical 1 by changing the voltage on a signal line during a cycle. Still others represent a logical 1 by a voltage pulse on a line during the cycle. Further, where a voltage transition during the cycle is used to represent a signal, the time at which that transition occurs might be different for different chips under test.
Modern testers arc sufficiently flexible that they can be programmed for almost any signal format. To achieve this flexibility, the tester includes a timing generator
122
. The timing generator generates what are known as “edge” signals. These are signals that change state at a time that can be programmed into the timing generator.
The edge signals are combined by a formatter
126
to produce an output signal of the desired shape. For example, to create a pulse that starts 0.5 nsec after the start of a cycle and has a width of 1 nsec, one of the edge signals would be programmed to occur 0.500 nsec after the start of the cycle. Another edge signal would be programmed to occur at 1.5 nsec after the start of the cycle. The formatter would combine these signals to create the desired signal to be applied to driver
128
. Driver
128
produces the signal that is applied to the device under test.
More specifically, formatter
126
uses the first edge to define when driver
128
is turned on and the second edge to define when driver
128
is turned off. Traditionally, the circuit that combines the edges is a S-R flip-flop. A S-R flip-flop has an Set input and a Reset input. While a logic high signal is applied to the Set input, the output of the flip-flop is high. While a logic high is applied to the Reset input, the output of the flip-flop is low. While both the Set and Reset inputs are low, the S-R flip-flop holds its state.
In a tester, the data in the pattern generator
120
controls which edges are applied to the flip flop in each cycle. For example, in a cycle in which the channel
114
should output a signal that is goes high at 0.5 nscec and low at 1.5 nsec, the tester will gate an edge to the S input of the flip flop that goes high at 0.5 nsec. Separately, an edge that goes high at 1.5 nsec is gated to the R input of the flip flop.
Because there are multiple edge signals which can all be programmed to occur at different times, the tester can be programmed to generate nearly any type of waveform. A limitation arises, though, when a very fast signal is to be generated.
An S-R flip-flop does not work in a tester when the signals at the S and R inputs are both high. Setting both the S and R inputs of a flip-flop high represents an invalid input condition. The flip-flop can not be simultaneously set and reset. In some flip-flop designs, setting both the S and R inputs high at the same time produces a random output. Other S-R flip-flop designs place the output of the flip-flop in a known state—either high or low—when both inputs are asserted.
In testers, this problem has been conventionally dealt with in two ways. First, the duration of the edge signals is made very short relative to the length of a tester period. In this way, the chance that edge signals will drive the S and R inputs of the flip-flop simultaneously will be reduced. However, this approach is not well suited for generating signals to test very fast chips. As the period gets smaller, the width of the edge signal would have to be very small for the edge signal to be only a small fraction of the period. It is difficult to make an accurate timing generator that operates at high data rates when the width of the edge signal must be very small.
The second way that the problem has been dealt with is by providing a timing specification. The specification provides a minimum the time that must be programmed between an edge that will be applied to the Set input of the flip-flop and the Reset input of the flip-flop to ensure that both edges are not high at the same time. However, this specification limits the width of the output pulses that can be generated by driver
128
. It would be desirable to allow driver
128
to generate very narrow pulses, particularly for testing high speed devices.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to provide a test system that can generate narrow output pulses.
The foregoing and other objects are achieved in a test system that employs a formatter with an improved flip-flop. The flip-flop provides the desired outputs even when its Set and Reset inputs overlap.
REFERENCES:
patent: 3686565 (1972-08-01), Kelem et al.
patent: 3947697 (1976-03-01), Archer et al.
patent: 4119910 (1978-10-01), Hayashi
“Synthesis Technique for CMOS Folded Source-Coupled Logic Circuits” Sailesh Maskai, et al. IEEE Journal of Solid State Circuits Aug. 1992, pp. 1157-1167.
Metjahic Safet
Nguyen Vincent Q.
Teradyne, Inc.
Walsh Edmund J.
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