Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Patent
1994-06-28
1995-10-24
Nguyen, Vinh P.
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
324 731, 371 223, G01R 3128
Patent
active
054613108
ABSTRACT:
A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.
REFERENCES:
patent: Re31056 (1982-10-01), Chau et al.
patent: 3478325 (1969-11-01), Oeters et al.
patent: 3633113 (1972-01-01), Grubel et al.
patent: 3976940 (1976-08-01), Chau et al.
patent: 4063308 (1977-12-01), Collins et al.
patent: 4079456 (1978-03-01), Lunsford et al.
patent: 4102491 (1978-07-01), DeVito et al.
patent: 4130866 (1978-12-01), Ono
patent: 4217639 (1980-08-01), Hartley et al.
patent: 4231104 (1980-10-01), St. Clair
patent: 4270116 (1981-05-01), Ichimiya et al.
patent: 4290133 (1981-09-01), Stewart et al.
patent: 4310802 (1982-01-01), Ichimiya et al.
patent: 4321687 (1982-03-01), Parsons et al.
patent: 4386401 (1983-05-01), O'Brien
patent: 4419739 (1983-12-01), Blum
patent: 4428042 (1984-01-01), Niethhammer et al.
patent: 4430826 (1984-02-01), Whiteside et al.
patent: 4451918 (1984-05-01), Gillette
patent: 4482983 (1984-11-01), Siechta, Jr.
patent: 4486832 (1984-12-01), Haubner et al.
patent: 4490821 (1984-12-01), Lacher
patent: 4497022 (1985-01-01), Cormier et al.
patent: 4517661 (1985-05-01), Graf et al.
patent: 4564953 (1986-01-01), Werking
patent: 4707834 (1987-11-01), Firsch et al.
patent: 4779221 (1988-10-01), Magliocco et al.
patent: 4789835 (1988-12-01), Herlein
patent: 4806852 (1989-02-01), Swan et al.
patent: 4827437 (1989-05-01), Blanton
patent: 4875006 (1989-10-01), Henley
patent: 4876501 (1989-10-01), Ardini et al.
patent: 4931723 (1990-06-01), Jeffrey et al.
patent: 5025205 (1991-06-01), Mydill et al.
patent: 5212443 (1993-05-01), West et al.
patent: 5274796 (1993-12-01), Conner
Barber, Satre, "Timing Accuracy in Modern ATE," IEEE Design & Test of Computers, pp. 22-30, Apr. 1987.
Herlein, "Optimizing The Timing Architecture Of A Digital LSI Test System," 1983 International Test Conference, pp. 200-209.
West, "Attainable Accuracy of Autocalibrating VLSI Test Systems," 1983 International Test Conference, pp. 193-199.
Grasso et al., A 250 MHz Test System's Timing and Automatic Calibration, 1987 International Test Conference, pp. 76-84.
Bissett, "Effective Use of Hardware in LSI Chip Testing," 3rd USA-Japan Computer Conference, Session 14-3-1, 1978.
Bissett, "The Development Of A Tester-Per-Pin VLSI Test System Architecture," 1983 International Test Conference, 151-155.
Catalano, Feldman, Krutiansky, Swan, "Individual Signal Path Calibration for Maximum Timing Accuracy In A High Pincount VLSI Test System," 1983 International Test Conference, pp. 188-192.
Foster, "Optimising vlsi test accuracy," Electronics Manufacture & Test, pp. 49-52, Dec. 1985.
Foster, "VLSI Tester Timing Accuracy Attached From The Top Down," Electronic Production Efficiency Exposition 85, pp. 14-20, 1985.
Kline, "VLSI Testers Help Guarantee Chip Quality," Electronics Week, pp. 63-66, Oct. 29, 1984.
Mullis, "An Expert System for VLSI Tester Diagnostics," 1984 International Test Conference, pp. 196-199.
"One Tester Handles ASIC and Commodity VLSI Chips," Electronics, pp. 98-99, May 14, 1987.
Swan, McMinn, "General-Purpose tester puts a separate set of resources behind each VLSI-device pin," Electronics, pp. 101-106, Sep. 8, 1983.
"VLSI Chip Test System Tests Itself At Board Level," Electronics, pp. 46-49, Aug. 5, 1985.
"VLSI tester has test electronics for every pin," Computer Design, pp. 56-60, Oct. 1983.
Sudo et al., "Ultimate": A 500-MHz VLSI Test System With High Timing Accuracy, 1987 International Test Conference, pp. 206-213.
West, Napier, "Sequencer Per Pin.TM. Test System Architecture," 1990 International Test Conference, pp. 355-361.
Sugamori et al., "Analysis And Definition Of Overall Timing Accuracy In VLSI Test System," IEEE Test Conference, pp. 143-153.
Deerr, "Automatic Calibration For A VLSI Test System," 1983 International Test Conference, pp. 181-186.
J937 Memory Test System Specifications, Teradyne, Jul. 28, 1987.
J971 VLSI Test System, System Description, Teradyne, Aug. 1991.
Skala, "Continual Auto-Calibration For High Timing Accuracy," 1980 IEEE Test Conference, pp. 111-116.
"Teradyne's Big Gamble In Test Equipment," Electronics, pp. 72-74, Nov. 13, 1986.
Mydill, "A Generic Procedure For Evaluating VLSI Test System Timing Accuracy," 1987 International Test Conference, pp. 214-225.
Healy, Ure, "A Method of Reducing ATE System Error Components and Guaranteeing Subnanosecond Measurement Accuracies," 1985 International Test Conference, pp. 191-202.
Pabst, "Timing Accuracy and Yield Estimation," 1986 International Test Conference, pp. 778-787.
Butner, "Evaluation of a prototype VLSI tester," Integration, the VLSI Journal 5 (1987), 275-288.
Milne, "Timing, not speed, counts the most when testing fast VLSI IC's," Electronic Design, pp. 132-142, May 29, 1986.
Cheung David K.
Graeve Egbert
Nguyen Vinh P.
Rowland Mark D.
Schlumberger Technologies Inc.
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