Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Patent
1990-09-05
1993-07-06
Nguyen, Vinh
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
324 731, 371 151, 371 223, G01R 3128
Patent
active
052257720
ABSTRACT:
A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.
REFERENCES:
patent: 4594544 (1986-06-01), Necoechea
patent: 4639919 (1987-01-01), Chang et al.
patent: 4642561 (1987-02-01), Groves et al.
patent: 4646299 (1987-02-01), Schinabeck et al.
patent: 4660197 (1987-04-01), Wrinn et al.
patent: 4682330 (1987-07-01), Millham
patent: 4724379 (1988-02-01), Hoffman
patent: 4727312 (1988-02-01), Fulks
patent: 4746855 (1988-05-01), Wrinn
patent: 4779221 (1988-10-01), Magliocco et al.
patent: 4792932 (1988-12-01), Bowhers et al.
patent: 4806852 (1989-02-01), Swan et al.
patent: 4809221 (1989-02-01), Magliocco et al.
patent: 4816750 (1989-03-01), Van der Kloot et al.
patent: 4857833 (1989-08-01), Gonzalez et al.
patent: 4875210 (1989-10-01), Russo et al.
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 4931723 (1990-06-01), Jeffrey et al.
"Teradyne's Tester For Tomorrow's VLSI", Electronics Nov. 13, 1986.
"`Ultimate`: A 500-MHz VLSI Test System with High Timing Accuracy", Tsuneta Sudo et al., NTT Electrical Communications Laboratories, Japan, Paper 8.2 1987 International Test Conference, 1987 IEEE.
"The Development Of A Tester-Per-Pin VLSI Test System Architecture", Steve Bisset, Megatest Corporation, Santa Clara, Calif., 1983 International Test Conference, Paper 6.2, 1963 IEEE.
Cheung David K.
Graeve Egbert
Nguyen Vinh
Schlumberger Technologies Inc.
LandOfFree
Automatic test equipment system using pin slice architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic test equipment system using pin slice architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic test equipment system using pin slice architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1692759