Boots – shoes – and leggings
Patent
1995-08-18
1998-09-08
Louis-Jacques, Jacques
Boots, shoes, and leggings
364488, 364489, 364491, 364578, G06F 1750, G06F 1710
Patent
active
058054626
ABSTRACT:
A method of automatic synthesis of an integrated circuit, comprising the steps, performed by a programmed machine, of storing a Boolean expression which expresses a combinatorial part of the said integrated circuit, factorizing the Boolean expression and mapping the factorized Boolean expression into a representation of said integrated circuit in hardware terms. The step of factorizing comprises computing a zero-suppressed binary decision diagram unique to and representing the Boolean expression; computing, from said ZBDD, candidate divisors of said expression; selecting candidate divisors; and dividing the Boolean expression by the candidate divisor. The selection of candidate divisors includes computing attributed value on the basis of the saving of literals. The method includes the use of implicit division comprising computing upper and lower bounds for a remainder and then a quotient.
REFERENCES:
patent: 5434794 (1995-07-01), Coudert et al.
patent: 5487017 (1996-01-01), Prasad et al.
O. Coudert and J.C. Madre, "Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions", 1992, pp. 36-39, 29th ACM/IEEE Design Automation Conference, 8 Jun. 1992.
Oliver Coudert, Jean Christophe Madre and Henri Fraisse, "A New Viewpoint on Two-Level Logic Minimization", 1993, pp. 625-630, 30th ACM/IEEE Design Automation Conference, 14-18 Jun. 1993.
Ted Stanion and Carl Sechen, "Boolean Divison and Factorization Using Binary Decision Diagrams", pp. 1179-1184, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 9, Sep. 1994.
Shin-ichi Minato, "Zero-Supporessed BDDs for Set Manipulation in Combinatorial Problems" NTT LSI Laboratories, pp. 1-6., 14-18 Jun. 1993.
Robert K. Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli and Albert R. Wang, "MIS: A Multiple-Level Logic Optimization System", pp. 1062-1081, IEEE Transactions on Computer-Aided Design, vol. Cad-6, No. 6, Nov. 1987.
Randal E. Bryant, "Graph-Based Algorithm for Boolean Function Manipulation", pp. 677-691, IEEE Transactions on Computers, vol. C-35, No. 8. Aug., 1986.
Stanion et al. ("Boolean Division and Factorization Using Binary Decision Diagram", IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems, vol. 13, No. 9, pp. 1179-1184), Sep. 1994.
Radivojevic et al. ("On Applicability of Symbolic Techniques to Larger Scheduling Problems", IEEE Proceedings of the European Design and Test Conference, pp. 1062-1081), Mar. 9, 1995.
Brayton et al. ("MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on Computer-Aided Design, vol. CAD-6, pp. 48-53), Nov. 1987.
Minato ("Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems", 30th ACM/IEEE Design Automation Conference, pp. 272-277), Jun. 14, 1993.
Hachtel et al. ("MUSE: A Multilevel Symbolic Encoding Algorithm for State Assignment", IEEE Transactions on Computer Aided Design, vol. 10, No. 1, pp. 28-38), Jan. 1991.
Malik et al. ("Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment", IEEE International Conference on Computer-Aided Design, ICCAD-88, pp. 6-9), Nov. 1988.
Poirot Frank
Roane Ramine
Tarroux Gerard
Kik Phallaka
Louis-Jacques Jacques
VLSI Technology Inc.
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