Automatic selection of an on-chip ancillary internal clock...

Details Automatic selection of an on-chip ancillary internal clock... Automatic selection of an on-chip ancillary internal clock...

2006-05-02

2006-05-02

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S407000, C327S099000

Reexamination Certificate

active

07038506

ABSTRACT:
A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

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