Automatic protocol synthesizing system

Details Automatic protocol synthesizing system Automatic protocol synthesizing system

1986-11-12

1989-01-31

Atkinson, Charles

Excavating

364900, G01R 3128, G06F 1531

Patent

active

048021628

ABSTRACT:
An automatic protocol synthesizing system in which, incomplete state transition diagrams of at least two functionally incomplete processes forming a protocol are received and completed state transition diagrams of the processes are outputted. In accordance with the present invention, there is provided a checking circuit for making a check for a logical error of the incomplete state transition diagram an embedding circuit embeds the state transition diagram of a process corresponding to the incomplete state transition diagram of an ith (where 1.ltoreq.i.ltoreq.N) one of the processes in the ith incomplete state transition diagram. A state transition diagram generating circuit is provided for automatically generating a state transition diagram including all of the remaining (i+1)th and subsequent processes, on the basis of the embedded state transition diagram; and a dividing circuit divides the thus automatically synthesized state transition diagram into the state transition diagram of the (i+1)th one of all the automatically generated processes and the state transition diagram for the other processes. The operations of the checking circuit, the embedding circuit, the state transition diagram generating circuit and the dividing circuit are repeated by (N-1) times to complete the state transition diagram for each process, thereby making the protocol functionally complete.

REFERENCES:
Cork et al., Automated Use of a Theoretical System Description in Practical Testing, IBM Technical Discl. Bulletin, vol. 19, No. 4, Sep. 1976, pp. 1446-1447.
Hayes, Transition Count Testing of Combinational Logic Circuits, IEEE Trans. on Computers, vol. C-25, No. 6, Jun. 1976, pp. 613-620.

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