Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-03-12
1998-05-12
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
36518901, 36518907, C11C 1300
Patent
active
057516375
DESCRIPTION:
BRIEF SUMMARY
The present application is related to PCT Application No. PCT/US95/00077, filed 5 Jan. 1995 entitled ADVANCED PROGRAM VERIFY FOR PAGE MODE FLASH MEMORY, which is related to U.S. Pat. No. 5,526,307, which is a continuation-in-part of U.S. patent application Ser. No. 08/187,118, filed Jan. 25, 1994, now U.S. Pat. No. 5,399,891; which is a continuation of U.S. Application No. 07/823,882, filed Jan. 22, 1992 now abandoned.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flash EEPROM memory technology, and more particularly to an improved flash EEPROM memory architecture for automatic programming with controlled programming voltages for improved efficiency and speed.
2. Description of Related Art
Flash EEPROMs are a growing class of non-volatile storage integrated circuits. The memory cells in a flash EEPROM are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material.
The floating gate may be charged through a Fowler-Nordheim tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected into the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism, known as hot electron injection, may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by an F-N tunneling mechanism between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the drain by establishing a large positive voltage from the drain to the gate, while the source is left at a floating potential.
The high voltages used to charge and discharge the floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size.
Furthermore, the act of charging and discharging the floating gate, particularly when using the F-N tunneling mechanism, is a relatively slow process that can restrict the application of flash memory devices in certain speed sensitive applications.
In state of the art floating gate memory architectures using sub-micron technology, the critical dimension variation in patterns on the physical material is usually controlled within about 10%. For a flash EEPROM cell, or other floating gate memory, such variation in critical dimensions may result in a variation in programming speed to the second order, using the Fowler Nordheim tunneling method. Further, if deviation in bias voltages in the array are considered, the variation in programming speed may vary by the fourth order in state of the art devices.
The conventional method to program flash memory uses a fixed pulse width and fixed bias, with a program verification loop executed after each programming pulse. If the verify fails, then another pulse is applied in an iterative fashion. If the programming pulses have too much energy, then over-programmed cells will result. If the pulses have too little energy, then an insufficient number of cells will be programmed in the first cycle. An over-programme
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Chen Chia Shing
Hung Chun-Hsiung
Kamei Teruhiko
Wan Ray-Lin
Fears Terrell W.
Macronix International Co. Ltd.
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