Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-06-26
2004-04-06
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185220
Reexamination Certificate
active
06717859
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronically erasable memory circuits, and in particular to methods and apparatus for analyzing physical and electrical properties of such circuits.
BACKGROUND
FIG. 1
depicts a conventional memory circuits
100
, including a sense amplifier
105
and an EEPROM cell
110
. Cell
110
includes an access transistor
112
, a storage transistor
114
, and a program transistor
116
. The source of program transistor
116
connects to the gate of storage transistor
114
via an insulating layer, typically referred to as a “tunnel oxide” layer
118
. Tunnel oxide layer
118
has a thickness T
OX
that is thin enough to permit electrons to tunnel to and from the gate of transistor
114
when the proper bias voltages are applied to various terminals of EEPROM cell
110
. Cell
110
also includes a capacitor
120
connected between the floating gate of transistor
114
and a control gate CG.
TABLE 1
Node
Program
Erase
Read/Verify
AG
V
PP
V
EE
V
DD
VGND
Z
0
0
CG
0
V
EE
V
DD
PCB
0
0
V
DD
PBL
V
PP
-V
t
0
V
t
RBL
Z
0
Data
As shown in Table 1 above, storage transistor
114
is programmed by simultaneously:
1. presenting high impedances (Z) on the source and drain of transistor
114
by turning transistor
112
on and disconnecting node RBL and VGND from external circuitry;
2. connecting the control terminal (gate) of transistor
114
through transistor
116
and tunnel oxide layer
118
to a programming voltage V
PP
−V
t
(the V
t
drop is due to a transistor, not shown, connected between the program/erase node V
PE
); and
3. holding control-gate node CG at zero volts.
The programming voltage V
PP
is high relative to the operating voltage V
DD
Of EEPROM cell
110
. For example, the programming voltage V
PP
might be about 14 volts for an EEPROM cell for which V
DD
is about 1.8 volts. With storage transistor
114
biased as listed above, electrons travel through the tunnel oxide
118
away from the gate of transistor
114
, leaving the gate with a relatively positive net charge. This charge shifts the threshold voltage V
T
(i.e., the voltage at which transistor
114
conducts the minimum current necessary to trip sense amplifier
110
) in the negative direction. The new “programmed” threshold voltage V
TP
is then less than V
DD
.
Referring again to Table 1, storage transistor
114
is erased by simultaneously:
1. applying a relatively high erase voltage V
EE
to the gate of storage transistor
114
via control-gate node CG;
2. applying a relatively low voltage to the program bit line PBL (the source of the low voltage is omitted); and
3. turning program transistor
116
on.
Thus biased, positive charge collected on the gate of storage transistor
114
is swept away through tunnel oxide
118
, shifting the threshold voltage of storage transistor
114
to an erase threshold voltage V
TE
above V
DD
.
The following Equation 1 summarizes the relationship between the program threshold voltage V
TP
, erase threshold voltage V
TE
, and supply voltage V
DD
:
V
TP
<V
DD
<V
TE
eq. (1)
Once programmed, cell
110
can be read by applying V
DD
to the access gate AG of transistor
112
, control gate CG, and pre-charge node /PC (the “/” designate an active low signal). Pre-charge node /PC is held low between reads to hold the input of a series of inverters
122
and
123
high, and consequently to hold the output node SA of sense amp
110
at a logic one. Pre-charge node /PC goes high during a read, connecting the input of inverter
122
to the read bit line RBL via a transistor
128
. If the threshold voltage of transistor
114
is above V
DD
, then the read bit line RBL will not conduct, and sense amp
105
will continue to output a high (logic one) output signal on sense amplifier output node SA. If, on the other hand, the threshold voltage of transistor
114
is below V
DD
, then transistors
112
and
114
will conduct with V
DD
applied to terminals AG and CG, and the resulting current through read bit line RBL will overcome the pre-charge in sense amp
105
, forcing the output node SA of sense amp
105
to transition to a logic zero.
Due to the relatively high program and erase voltages, some transistors in circuit
100
are high-voltage transistors, as conventionally indicated using an additional line segment in parallel with the gates of those transistors.
In addition to programming and erasing storage cell
114
, the supporting circuitry should also be able to verify program and erase states. As noted above, the programmed threshold voltage V
TP
of transistor
114
is V
DD
and the erase threshold voltage V
TE
is above V
DD
. Moreover, the program and erase threshold voltages are sufficiently different from V
DD
to provide a guard band that allows for operating changes due to power-supply and temperature fluctuations.
The need for guard bands might lead one to conclude that the voltage range between the program threshold voltage V
TP
and the erase threshold voltage V
TE
(i.e., the “cell margin”) should be as large as possible. However, the relatively high program and erase voltages required to maximize the cell margin tend to limit cell life. Moreover, maximizing the cell margin means increasing program and erase times, and keeping these times short is of considerable interest to customers. Manufacturers of EEPROM cells are therefore interested in identifying a program/erase margin that provides a desired balance between program and erase speeds, device lifetime, and insensitivity to errors.
A problem that arises when selecting an appropriate cell margin for a given collection of memory cells is that process variations can have a substantial impact on program and erase threshold voltages. One parameter that is particularly important is the oxide thickness T
OX
of tunnel oxide
118
. Experiments have shown that even relatively small changes in oxide thickness can have significant impacts on program and erase threshold voltages. It is therefore important to determine—often for each wafer—the program and erase voltages required to produce a desired margin. Unfortunately, assessing an individual wafer to optimize program and erase voltages can be difficult and time consuming. There is therefore a need for a more effective means of optimizing applied program and erase voltage levels to provide desired cell margins.
SUMMARY
Described are circuits and methods for automatically measuring the program threshold voltage V
TP
and the erase threshold voltage V
TE
of EEPROM cells. The measured threshold voltages are employed to measure tunnel-oxide thickness and to determine optimal program and erase voltage levels for EEPROM circuits. One embodiment automatically sets the program and erase voltages based on the measured threshold voltages, and thus eliminates the labor intensive task of iteratively determining and setting optimal program and erase voltages.
This summary does not limit the invention, which is instead defined by the claims.
REFERENCES:
patent: 5023839 (1991-06-01), Suzuki et al.
patent: 5563827 (1996-10-01), Lee et al.
patent: 5661685 (1997-08-01), Lee et al.
patent: 5905691 (1999-05-01), Tanzawa et al.
patent: 6469924 (2002-10-01), Jain
patent: 6469925 (2002-10-01), Jain
Davies, Jr. Thomas J.
Om'Mani Henry A.
Auduong Gene
Behiel Arthur J.
Xilinx , Inc.
Young Edel M.
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