Automatic placement method for arranging logic cells

Details Automatic placement method for arranging logic cells Automatic placement method for arranging logic cells

1991-01-22

1992-08-18

Mintel, William

Boots, shoes, and leggings

357 40, 364491, H01L 2710

Patent

active

051404028

ABSTRACT:
An automatic placement method for arranging logic cells on a chip, having a setting step for setting an evaluation function, target values thereof, placement improvement methods, and a range of a satisfaction level of each evaluation function, a calculating step for calculating a difference between a value of each evaluation function and, its target value, an improving step for selecting one of the placement improvement methods to optimize the evaluation function having the largest difference and then executing the placement improvement method; wherein the above processing is repeatedly executed over a required number of times, the range of each evaluation function is set by using probabilistic fluctuation each processing, and the range of each evaluation function is further narrowed with every processing.

REFERENCES:
patent: 4580228 (1986-04-01), Noto
patent: 4686629 (1987-08-01), Noto et al.

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