Automatic pin circuitry shutoff for an integrated circuit

Details Automatic pin circuitry shutoff for an integrated circuit Automatic pin circuitry shutoff for an integrated circuit

1990-12-18

1992-07-28

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 307475, 307540, 324 731, 324158R, H03K 1716, G01R 3128

Patent

active

051343142

ABSTRACT:
A method and circuitry allows for the prevention of tester induced failures and reliability problems which occur when a tester creates bus contention by overdriving output pins of an integrated circuit. For each input/output (I/O) pad which is used for the output of data, a first signal on an output data line is compared with a second signal which is currently on the I/O pad. When the output is enabled and the comparison indicates the first signal is not equal to the second signal, the I/O pad is isolated from the output data line. The I/O pad is isolated, and thus in shutdown mode, until the I/O pad is no longer being driven to a signal value which is different than the signal value of the first signal on the output data line. Further, each I/O pad may be electrically isolated from its output data line whenever a comparison for any I/O pad indicates that the signal for the I/O pad is not equal to the signal on its output data line. In one embodiment, once all of the I/O pads is in shutdown mode, they are held in shutdown mode until a reset signal is received.

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