Oscillators – Automatic frequency stabilization using a phase or frequency... – Transistorized controls
Reexamination Certificate
2007-12-04
2007-12-04
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Transistorized controls
C716S030000
Reexamination Certificate
active
10810444
ABSTRACT:
A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5055716 (1991-10-01), El Gamel
patent: 5289021 (1994-02-01), El Gamal
patent: 5633807 (1997-05-01), Fishburn et al.
patent: 5754826 (1998-05-01), Gamal et al.
patent: 5973524 (1999-10-01), Martin
patent: 6002860 (1999-12-01), Voinigescu et al.
patent: 6269277 (2001-07-01), Hershenson et al.
patent: 6311145 (2001-10-01), Hershenson et al.
patent: 6311315 (2001-10-01), Tamaki
patent: 6381563 (2002-04-01), O'Riordan et al.
patent: 6425111 (2002-07-01), del Mar Hershenson
patent: 6532569 (2003-03-01), Christen et al.
patent: 6539533 (2003-03-01), Brown, III et al.
patent: 6574786 (2003-06-01), Pohlenz et al.
patent: 6577992 (2003-06-01), Deng et al.
patent: 6578179 (2003-06-01), Shirotori et al.
patent: 6581188 (2003-06-01), Hosomi et al.
patent: 6588002 (2003-07-01), Lampaert et al.
patent: 6813590 (2004-11-01), Crusius
patent: 6909330 (2005-06-01), Colleran et al.
patent: 2004/0172609 (2004-09-01), Hassibi et al.
patent: WO 01/37429 (2001-05-01), None
Chan, Shu-Park; “Analysis of Linear Networks and Systems”, Addison-Wesley Publishing Company, 1972, pp. 23-25, 46 and 47.
Kortanek, K.O., et al., “An Infeasible Interior-Point Algorithm For Solving Primal and Dual Geometric Programs,” pp., 155-181, Mathematical Programming Society, Inc., 76:155-181, Jan. 1, 1995.
Gielen, G., et al., “An Analogue Module Generator For Mixed Analogue/Digital ASIC Design”, International Journal of Circuit Theory and Applications, vol. 23, pp. 269-283, 1995.
Hershenson, M., et al., “Automated Design of Folded-Cascode Op-Amps with Sensitivity Analysis”, pp. 121-124, Electronics, Circuits and Systems, IEEE International Conference on LISBOA, Sep. 7-10, 1998.
Hershenson, M., et al., “Optimization of Inductor Circuits via Geometric Programming”, pp. 994-998, Design Automation Conference, Jun. 21, 1999, Proceedings.
Mediero, F., et al., “A Vertically Integrated Tool For Automated Design Of Sigma Delta Modulators”, IEEE Journal of Solid-State Circuits, vol. 30., No. 7, Jul. 1, 1995, pp. 762-767.
Hershenson, M., et al., “Optimal Design Of A CMOS Op-Amp Via Geometric Programming”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 20., N. Jan. 1, 2001, pp. 1-21.
Mandal, P., et al., “CMOS Op-Amp Sizing Using A Geometry Programming Formulation”, IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, vol. 20., No. 1, Jan. 31, 2001, pp. 22-38.
Daems, W., et al., “Simulation-based Automatic Generation Of Signomial And Posynomial Performance Models For Analog Integrated Circuit Sizing”, IEEE/ACM International Conference On Computer-Aided Design, Nov. 4, 2001, pp. 70-74.
Von Kaenel, V., et al., “A 320MHz, 1.5mW at 1.36V CMOS PLL For Microprocessor Clock Generation”, IEEE Solid-State Circuits Conference, Feb. 9, 1996, Digest of Technical Papers, 42nd ISSCC96/ Session 8 / Digital Clock and Latches / Paper FA 8.2.
Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessor”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Novof, et al., “Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and + 50 ps Jitter”, IEEE Journal of Solid-State Circuits, vol. 30., No. 11, Nov. 1995, pp. 1259-1266.
Mohan, et al., “Simple Accurate Expressions for Planar Spiral Inductances”, IEEE Journal of Solid-State Circuits, vol. 34, No. 10, Oct. 1999, pp. 1419-1424.
Hershenson, “CMOS Analog Circuit Design Via Geometric Programming”, A Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University, Nov. 2003, 235 pages.
Hershenson, M., et al., “GPCAD: A Tool for CMOS Op-Amp Synthesis” 8 pages, Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 296-303, Nov. 1998.
Hershenson, M., et al., “Posynomial models for MOSFETs” 9 pages, Jul. 7, 1998.
Chang, H, et al., “A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits” 6 pages, IEEE 1992 Custom Integrated Circuits Conference.
Chavez, J., et al, “Analog Design Optimization: A Case Study” 3 pages, IEEE, Jan. 1993.
Geilen, G., et al., “Analog Circuit Design Optimization Based on Symbolic Simulation and Simulated Annealing”, pp. 707-713, IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun. 1990.
Fishburn, J, et al., “TILOS: A Posynomial Programming Approach to Transistor Sizing” pp. 326-328, IEEE, 1985.
Maulik, P., et al., “Integer Programming Based on Topology Selection of Cell-Level Analog Circuits”, 12 pages, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, vol. 14, No. 4, Apr. 1995.
Swings, K., et al., “An Intelligent Analog IC Design System Based On Manipulation Of Design Equations” pp. 8.6.1-8.6.4, IEEE 1990, Custom Integrated Circuits Conference.
Nesterov, Y., et al., “Interior-Point Polynomial algorithms in Convex Programming” 8 pgs., 1994, Society for industrial and Applied mathematics.
Yang, H.Z., et al., “Simulated Annealing Algorithm with Multi-Molecule: an Approach to Analog Synthesis” pp. 571-575, IEEE, 1996.
Wong, D.F., et al., “Simulated Annealing For VLSI Design” 6 pages, 1998, Kulwer Academic Publishers.
Maulik, P., et al., “Sizing of Cell-Level Analog Circuits Using Constrained Optimization Techniques” pp. 233-241, IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993.
Ochotta, E, et al., “Synthesis of High -Performance Analog Circuits in ASTRX/OBLS” pp. 273-295, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, vol. 15, No. 3, Mar. 1996.
Wright, S., “Primal-Dual Interior-Point Methods” pp. 1-3, http://www.siam.org/books/wright, Printed Aug. 19, 1998.
Shyu, J., et al., “Optimization-Based Transistor Sizing” pp. 400-408, IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1998.
Wright, S., “Primal-Dual Interior-Point Methods” 14 pages, 1997, Society for Industrial and Applied Mathematics.
Van Laarhoven, P.J.M., et al., “Simulated Annealing: Theory and Applications” 26 pages, 1987, Kulwer Academic Publishers.
Hershenson, M., et al., “CMOS Operational Amplifier Design and Optimization via Geometric Programming” pp. 1-4, Analog Integrated Circuits, Stanford University.
Aguirre, M.A., et al., “Analog Design Optimization by means of a Tabu Search Approach” pp. 375-378.
Medeiro, F., et al., “A Statistical Optimization-Based Approach for Automated Sizing of Analog Cells”, pp. 594-597, Dept. of Analog Circuit Design.
Spatnekar, S., “Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff” 27 pages, Dept. of Electrical and Computer Engineering.
Su, H., et al., “Statistical Constrained Optimization of Analog MOS Circuits Using Empirical Performance Models” pp. 133-136.
Vassiliou, I., et al, “A Video Driver System Designed Using a Top-Down, Constraint-Driven Methodology” 6 pages.
Sapatnekar, S, et al., “An Exact Solution to the Transistor Sizing Problems for CMOS Circuits Using Convex Optimization” 35 pages.
Bowman, R., “An Imaging Model For Analog Macrocell Layout Generation”, IEEE International Symposium On Circuits And Systems, vol. 2, May
Colleran Dave
Hassibi Arash
Mis David
Sabio Labs, Inc.
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